Soldering an electronics package to a motherboard

• US 7,357,293 B2
• Filed: 03/24/2004
• Issued: 04/15/2008
• Est. Priority Date: 03/24/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Suh, Daewoong
• Primary Examiner(s): STONER, KILEY SHAWN
• Application Number:
  US10/808,192
• Publication Number:
  US 20050210673A1
• Time in Patent Office: 1,483 Days
• Field of Search: None
• US Class Current: 228/180.21
• CPC Class Codes: H05K 2201/10992 Using different connection materials, e.g. different solders, for the same connection
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3463 Solder compositions in relation to features of the printed circuit board or the mounting process
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base

Abstract

In some example embodiments, a method includes engaging a first contact on a motherboard with a second contact on an electronic package. A portion of one of the first and second contacts is covered with an interlayer that has a lower melting temperature than both of the first and second contacts. The method further includes bonding the first contact to the second contact by melting the interlayer to diffuse the interlayer into the first and second contacts. The bonded first and second contacts have a higher melting temperature than the interlayer before melting. In other example embodiments, an electronic assembly includes a motherboard having a first contact that is bonded to a second contact on an electronic package. An interlayer is diffused within the first and second contacts such that they have a higher melting temperature than the interlayer before the interlayer is diffused into the first and second contacts.

Claims

1. A method comprising:

engaging a first contact on a motherboard with a second contact on an electronic package that includes a die bonded to a substrate, a portion of one of the first and second contacts being covered with an interlayer that has a lower melting temperature than the first and second contacts; and

bonding the first contact to the second contact by melting the interlayer to diffuse the interlayer into the first and second contacts, the bonded first and second contacts having a higher melting temperature than the interlayer before melting.

2. The method of claim 1 wherein bonding the first contact to the second contact includes exposing the interlayer and the first and second contacts to an environment having a temperature greater than the melting temperature of the interlayer but below the melting temperature of the first and second contacts.

3. The method of claim 2 wherein exposing the interlayer and the first and second contacts to an environment having a temperature greater than the melting temperature of the interlayer but below the melting temperature of the first and second contacts includes maintaining the interlayer and the first and second contacts within the environment until a portion of the interlayer diffuses into the first and second contacts.

4. The method of claim 3 wherein maintaining the interlayer and the first and second contacts within the environment until a portion of the interlayer diffuses into the first and second contacts includes maintaining the interlayer and the first and second contacts within the environment until a majority of the interlayer diffuses into the first and second contacts.

5. The method of claim 4 wherein maintaining the interlayer and the first and second contacts within the environment until a majority of the interlayer diffuses into the first and second contacts includes maintaining the interlayer and the first and second contacts within the environment until the interlayer is substantially diffused into the first and second contacts.

6. The method of claim 2 wherein exposing the interlayer and the first and second contacts to an environment includes exposing the interlayer and the first and second contacts to the environment for a period of time.

7. The method of claim 6 wherein exposing the interlayer and the first and second contacts to the environment for a period of time includes exposing the interlayer and the first and second contacts to the environment until the interlayer melts and then solidifies within the first and second contacts.

8. The method of claim 1 wherein engaging a first contact on a motherboard with a second contact on an electronic package includes pressing the first contact against the second contact.

9. The method of claim 1 wherein bonding the first contact to the second contact includes exposing the interlayer and the first and second contacts to an environment having a temperature less than 125 degrees Centigrade.

10. The method of claim 1 further comprising covering the portion of one of the first and second contacts with the interlayer.

11. The method of claim 10 wherein covering the portion of one of the first and second contacts with the interlayer includes covering a portion of both of the first and second contacts with the interlayer.

12. The method of claim 10 wherein covering the portion of one of the first and second contacts with the interlayer includes covering all exposed portions of one of the first and second contacts with the interlayer.

13. The method of claim 10 wherein covering the portion of one of the first second contacts includes electroplating the interlayer onto the portion of one of the first and second contacts.