Thin array plastic package without die attach pad and process for fabricating the same

• US 7,358,119 B2
• Filed: 01/12/2005
• Issued: 04/15/2008
• Est. Priority Date: 01/12/2005
• Status: Active Grant

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: ASAT Company Limited
• Inventors: Tsang, Kwok Cheung, Kwan, Kin Pui, Pedron, Serafin, McLellan, Neil, Higgins, Leo M. III
• Primary Examiner(s): Everhart; Caridad
• Application Number:
  US11/033,928
• Publication Number:
  US 20060154403A1
• Time in Patent Office: 1,189 Days
• Field of Search: 438/674, 438/116, 438/127, 438/673, 257/E21.502, 257/E21.503, 257/E21.506
• US Class Current: 438/127
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip

Abstract

A process for fabricating an integrated circuit package. Metal is plated up on a substrate to provide a plurality of contact pads and a plurality of fiducial markings on a periphery of the contacts. A transparent mask is selectively deposited on the substrate, over the fiducial markings. A semiconductor die is mounted on the substrate such that the contact pads circumscribe the semiconductor die and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds are encapsulated and the semiconductor die and contact pads are covered in a molding material. The substrate is selectively etched to thereby etch away the substrate underneath the contact pads and the semiconductor die. The integrated circuit package is singulated from other integrated circuit packages by sawing using the fiducial markings.

Claims

1. A process for fabricating an integrated circuit package, comprising:

selectively plating up metal on a substrate to provide a plurality of contacts pads and a plurality of fiducial markings on a periphery of said contact pads;

selectively depositing a transparent mask on said substrate, over said fiducial markings;

mounting a semiconductor die on said substrate such that said contact pads circumscribe said semiconductor die;

wire bonding said semiconductor die to ones of the contact pads;

encapsulating the wire bonds and covering the semiconductor die and contact pads in a molding material;

thereby etching away the substrate underneath said contact pads and said semiconductor die;

singulating said integrated circuit package from other integrated circuit packages by sawing using said fiducial markings.

2. The process according to claim 1 wherein said mounting comprises mounting said semiconductor die using a black epoxy, said black epoxy being exposed after said selective etching said substrate.

3. The process according to claim 1, wherein said selectively plating comprises selectively plating a plurality of layers of metal on said substrate.

4. The process according to claim 1, wherein said selectively plating comprises:

depositing a plating mask on a first surface of said substrate;

patterning said plating mask to expose selected portions of the first surface of the substrate;

electroplating successive layers of metal on said selected portions of the first surface of the substrate; and

stripping a remainder of said plating mask.

5. The process according to claim 1, further comprising depositing solder bumps on said contact pads after selectively etching said substrate.

6. The process according to claim 1, further comprising mounting said substrate to a carrier prior to singulating, wherein said singulating comprises sawing through said molding material and said substrate without sawing entirely through said carrier.

7. The process according to claim 6, wherein said carrier comprises a tape having an adhesive side to which said substrate is mounted.

8. The process according to claim 6, wherein said carrier comprises a carrier ring backed with an adhesive tape, said carrier ring having a void in which said adhesive tape is exposed such that said mounting said substrate comprises mounting said substrate to said adhesive tape in said void.

9. The process according to claim 8, further comprising punching out a portion of said carrier ring including said substrate, after singulating to provide a singulated integrated circuit package along with said other integrated circuit packages.

10. A process for fabricating a plurality of integrated circuit packages comprising:

selectively plating up metal on a substrate to provide a plurality of sets of contacts pds;

mounting a plurality of semiconductor dice on said substrate, each one of said semiconductor dice being circumscribed by a respective one of said sets of contact pads;

wire bonding said semiconductor dice to contact pads of respective ones of said sets of contact pads;

encapsulating said wire bonds and covering the semiconductor dice and sets of contact pads in a molding material;

selectively etching said substrate thereby etching away the substrate underneath said contact pads and said semiconductor dice;

mounting said substrate to a tape in a void in a carrier frame;

singulating said integrated circuit packages by sawing through said molding material and said substrate without sawing entirely through said tape and said carrier to provide a plurality of integrated circuit packages.

11. The process according to claim 10, further comprising punching out a portion of said carrier frame including said adhesive to provide a strip including said integrated circuit packages.

12. The process according to claim 10, wherein said mounting said plurality of said semiconductor dice comprises mounting said plurality of said semiconductor dice using a black epoxy, said black epoxy being exposed after said selective etching of said substrate.

13. The process according to claim 10, further comprising strip testing of said integrated circuit packages prior to mounting said substrate to said tape.

14. The process according to claim 10, further comprising laser marking of upper surfaces of said packages after encapsulating.

15. The process according to claim 10, further comprising depositing solder bumps on said contact pads after selectively etching.

16. The process according to claim 10, wherein said selectively plating up metal includes plating up metal on said substrate to provide a plurality of fiducial markings on a periphery of said sets of contacts.

17. The process according to claim 16, further comprising selectively depositing a transparent mask on said substrate, over said fiducial markings and wherein said singulating is carried out by sawing using said fiducial markings.

18. A strip including a plurality of integrated circuit packages, the strip comprising:

a plurality of semiconductor dice;

a plurality of sets of contact pads, each set of contact pads circumscribing a respective one of said semiconductor dice;

a plurality of wire bonds connecting said semiconductor dice to contact pads of respective ones of said sets of contact pads;

a molding material encapsulating said wire bonds and covering the semiconductor dice and sets of contact pads;

a substrate extending around a margin of said molding material, the substrate having an aperture therein in which a surfaces of said contact pads and said molding material are exposed;

a plurality of fiducial markings on said substrate;

a carrier backed by a tape, said substrate being mounted in a void in said carrier, to said tape; and

a plurality of saw grooves singulating said integrated circuit packages,

wherein said saw grooves extend through said molding material and said substrate, ending at said tape such that said saw grooves extend at most only partly through said tape.

19. The strip according to claim 18, further comprising a black epoxy on an underside of said semiconductor dice such that said black epoxy is exposed in said aperture in said substrate.

20. The strip according to claim 18, wherein said tape is an ultraviolet curable adhesive tape.

21. The strip according to claim 18, further comprising a plurality of solder bumps on said contact pads.

22. The strip according to claim 18, wherein said substrate includes a transparent mask thereon.

23. The strip according to claim 22, wherein said fiducial markings are visible through said transparent mask.

24. The strip according to claim 22, wherein said transparent mask is a transparent solder mask.