Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM

• US 7,358,120 B2
• Filed: 02/07/2007
• Issued: 04/15/2008
• Est. Priority Date: 09/12/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Koburger, Charles W. III, Hakey, Mark C., Furukawa, Toshiharu, Horak, David V., Holmes, Steven J., Mandelman, Jack A.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US11/672,251
• Publication Number:
  US 20070128813A1
• Time in Patent Office: 433 Days
• Field of Search: 438/128, 257/390, 257/E27.102, 257/E21.662, 257/E21.671
• US Class Current: 438/128
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/27 ROM only

Abstract

A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Claims

1. A method of fabricating a Read Only Memory (ROM) on a silicon-on-insulator (SOI) wafer, said method comprising the steps of:

a) forming a plurality of stripes oriented in a first direction in a silicon surface layer;

b) undercutting ones of said plurality of stripes, cavities being formed along at least one edge of said ones;

c) filling said cavities with a conductive material;

d) forming a plurality of diffusions in an upper surface of said ones, said diffusions forming diodes in said upper surface;

e) forming a plurality of conductive contacts, each of said plurality of conductive contacts contacting one of said diodes at said upper surface; and

f) forming a plurality of conductive lines in a second direction orthogonal to said first direction, a ROM cell being located at each intersection of one of said plurality of conductive lines with one of said plurality of silicon stripes.

2. A method of forming a ROM on a SOI wafer as in claim 1, wherein said plurality of stripes are formed in step (a) by opening trenches through said silicon surface layer and step (b) of undercutting comprises:

i) forming protective sidewalls along said plurality of stripes; and

ii) etching exposed insulator in said trenches below each said at least one edge.

3. A method of forming a ROM on a SOI wafer as in claim 2, wherein the step (c) of filling cavities comprises:

i) forming a conformal layer of conductive material on said SOI wafer; and

ii) directionally etching said conformal layer, surface areas of said conformal layer being removed and said conductive material remaining in said cavities.

4. A method of forming a ROM on a SOI wafer as in claim 2, wherein said protective sidewalls are formed along both sides of said plurality of stripes, said exposed insulator is etched on said both sides, and an exposed surface in each of said cavities is doped before filling with conductive material such that said conductive material forms a resistive contact with the doped said exposed surface.

5. A method of forming a ROM on a SOI wafer as in claim 4, wherein said exposed insulator is etched on said both sides until cavities forming on both sides meet under each of said plurality of stripes.

6. A method of fabricating an Integrated Circuit (IC) including a Read Only Memory (ROM), said method comprising the steps of:

a) forming a plurality of stripes oriented in a first direction in a semiconductor layer;

b) forming straps along the underside of each stripe;

c) forming at least one diode in an upper surface at least one stripe;

d) selectively forming conductive contacts to upper surfaces of said plurality of stripes; and

e) forming a plurality of conductive lines in a second direction orthogonal to said first direction, a ROM cell being located at each intersection of one of said plurality of conductive lines with one of said plurality of stripes.

7. A method of forming an IC as in claim 6, wherein the step (a) of forming said plurality of stripes comprises:

i) forming a pad layer on an upper surface of said semiconductor layer;

ii) patterning stripes in said pad layer;

iii) etching exposed said semiconductor layer; and

iv) removing the patterned said pad layer.

8. A method of forming an IC as in claim 6, wherein the step (b) of forming straps comprises:

i) undercutting ones of said plurality of stripes, cavities being formed along at least one edge of said ones; and

ii) filling said cavities with a conductive material.

9. A method of forming an IC as in claim 8, wherein said IC is a CMOS IC on a silicon-on-insulator (SOI) wafer, said semiconductor layer is a silicon surface layer and the step (i) of undercutting comprises:

A) forming protective sidewalls along said plurality of stripes; and

B) etching exposed insulator in said trenches below each said at least one edge.

10. A method of forming an IC as in claim 9, wherein said protective sidewalls are formed along both sides of said plurality of stripes, said exposed insulator is etched on said both sides, and an exposed surface in each of said cavities is doped before filling with conductive material such that said conductive material forms a resistive contact with the doped said exposed surface.

11. A method of forming an IC as in claim 9, wherein said exposed insulator is etched on said both sides until cavities forming on both sides meet under each of said plurality of stripes.

12. A method of forming an IC as in claim 8, wherein said IC is a CMOS IC on a silicon-on-insulator (SOI) wafer, said semiconductor layer is a silicon surface layer and the step (ii) of filling cavities comprises:

A) forming a conformal layer of conductive material on said SOI wafer; and

B) directionally etching said conformal layer, surface areas of said conformal layer being removed and said conductive material remaining in said cavities.

13. A method of forming an IC as in claim 12, wherein said conformal layer is a layer of doped polysilicon.

14. A method of forming an IC as in claim 6, wherein step (c) comprises forming diffusions in said upper surface at each ROM cell location, ROM cell contents being determined by selectively formed conductive contacts formed in step (d).

15. A method of forming an IC as in claim 6, wherein step (d) comprises forming conductive contacts at each ROM cell location, ROM cell contents being determined by diffusions in said upper surface formed in step (c).

16. A method of fabricating a silicon-on-insulator (SOI) Integrated Circuit (IC) including a Read Only Memory (ROM), said method comprising the steps of:

a) forming a plurality of trenches through a silicon surface layer oriented in a first direction, said plurality of trenches defining silicon stripes;

b) undercutting ones of said silicon stripes, cavities being formed along at least one edge of said ones;

c) filling said cavities with a conductive material;

d) selectively forming diodes in an upper surface of said silicon stripes;

e) selectively forming a conductive contact to each of said diodes; and

f) forming a plurality of metal lines in a second direction orthogonal to said first direction, a ROM cell being located at each intersection of one of said plurality of metal lines with one of said plurality of silicon stripes, ROM cell contents being determined by connection of a metal line to an underlying diode.

17. A method of forming a SOI IC as in claim 16, wherein step (d) comprises forming diffusions in said upper surface at each ROM cell location, ROM cell contents being determined by selectively formed conductive contacts formed in step (e).

18. A method of forming a SOI IC as in claim 16, wherein step (e) comprises forming conductive contacts at each ROM cell location, ROM cell contents being determined by diodes in said upper surface selectively formed in step (d).

19. A method of forming a SOI IC as in claim 16, wherein said SOI IC is a CMOS IC and the step (b) of undercutting comprises:

i) forming protective sidewalls along said silicon stripes; and

ii) etching exposed insulator in said trenches below each said at least one edge.

20. A method of forming a CMOS IC as in claim 19, wherein said exposed insulator is etched on said both sides until cavities forming on both sides meet under each of said silicon stripes.

21. A method of forming a CMOS IC as in claim 19, wherein the step (c) of filling cavities comprises:

i) forming a conformal layer of conductive material on said SOI wafer; and

ii) directionally etching said conformal layer, surface areas of said conformal layer being removed and said conductive material remaining in said cavities.

22. A method of forming a CMOS IC as in claim 21, wherein said protective sidewalls are formed along both sides of said stripes stripes, said exposed insulator is etched on said both sides, and an exposed surface in each of said cavities is doped before filling with conductive material such that said conductive material firms a resistive contact with the doped said exposed surface.