Tri-gate devices and methods of fabrication

• US 7,358,121 B2
• Filed: 08/23/2002
• Issued: 04/15/2008
• Est. Priority Date: 08/23/2002
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Datta, Suman, Barlage, Douglas
• Primary Examiner(s): Doan; Theresa T
• Application Number:
  US10/227,068
• Publication Number:
  US 20040036126A1
• Time in Patent Office: 2,062 Days
• Field of Search: 438/149, 438/176, 438/197, 438/283, 438/304, 438/157
• US Class Current: 438/149
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/482 the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Claims

1. A method of forming a transistor comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a continuous gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body, the gate electrode having laterally opposite sidewalls that run perpendicular to the laterally opposite sidewalls of the semiconductor body, and wherein the gate electrode provides a first gate adjacent to the top surface of the semiconductor body, a second gate adjacent to one of the laterally opposite sidewalls of the semiconductor body, and a third gate adjacent to the other of the laterally opposite sidewalls of the semiconductor body;

forming a sidewall spacer on each of the laterally opposite sidewalls of said gate electrode; and

forming a semiconductor film on and around said semiconductor body and adjacent to said sidewall spacers.

2. The method of claim 1 further comprising forming a silicide on said semiconductor film formed on said semiconductor body.

3. The method of claim 1 wherein said semiconductor film is formed by a selective deposition process.

4. A method of forming a semiconductor device comprising:

forming a first semiconductor body and a second semiconductor body on a substrate, said first and second semiconductor bodies each having a top surface and laterally opposite sidewalls and an insulating layer formed between said first and said second semiconductor bodies;

forming a first continuous gate dielectric layer on said top surface of said first semiconductor body and on said laterally opposite sidewalls of said first semiconductor body and forming a second continuous gate dielectric layer on the top surface of the second semiconductor body and on the laterally opposite sidewalls of the second semiconductor body;

forming a gate electrode on said gate dielectric layers on said top surface of said first and second semiconductor bodies and adjacent to said gate dielectric layers on said laterally opposite sidewalls of said first and second semiconductor bodies, said gate electrode formed above said insulating layer between said first and said second semiconductor bodies, wherein the gate electrode provides a pair of first gates adjacent to the top surfaces of the first and second semiconductor bodies, a pair of second gates adjacent to one of the laterally opposite sidewalls of each of the first and second semiconductor bodies, and a pair of third gates adjacent to the other of the laterally opposite sidewalls of each of the first and second semiconductor bodies;

forming a first source region and a first drain region in said first semiconductor body on opposite sides of said gate electrode;

forming a second source region and a second drain region in said second semiconductor body on opposite sides of said gate electrode;

forming a source landing pad which connects said first source region and said second source region; and

forming a drain landing pad which connects said first drain region and said second drain region.

5. The method of claim 4 wherein said top surface of said semiconductor body is separated from said substrate by a first distance and wherein said laterally opposite sidewalls of said semiconductor bodies are separated by a second distance and wherein said gate electrode has a pair of laterally opposite sidewalls separated by a third distance, wherein said first, second and third distance are substantially equal.

6. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a continuous gate dielectric layer on said top surface and on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode on said gate dielectric layer on said top surface of said semiconductor body and adjacent to said gate dielectric layer on said laterally opposite sidewalls of said semiconductor body, the gate electrode having laterally opposite sidewalls that run perpendicular to the laterally opposite sidewalls of the semiconductor body, and wherein the gate electrode provides a first gate adjacent to the top surface of the semiconductor body, a second gate adjacent to one of the laterally opposite sidewalls of the semiconductor body, and a third gate adjacent to the other of the laterally opposite sidewalls of the semiconductor body;

forming a pair of source/drain extensions in said semiconductor body on opposite sides of said gate electrode;

forming a pair of sidewall spacers on opposite sides of said laterally opposite sidewalls of said gate electrode and on said source/drain extensions in said semiconductor body;

forming a halo region in said semiconductor body beneath said gate electrode;

forming a semiconductor film on and around said semiconductor body adjacent to said sidewall spacer; and

forming a pair of source/drain contact regions in said semiconductor body adjacent to said sidewall spacers.

7. The method of claim 6 further comprising forming a semiconductor film on and around said semiconductor body adjacent to said sidewall spacer.

8. The method of claim 7 wherein said semiconductor film is silicon and said semiconductor body is silicon.

9. The method of claim 8 further comprising forming silicide on said silicon film formed on said silicon body.

10. The method of claim 6 wherein said source/drain extensions are formed by ion implantation.

11. The method of claim 6 wherein said pair of source/drain contact regions are formed by ion implantation.

12. A method of forming a transistor comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

forming a continuous gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode on said gate dielectric on the top surface of the semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body, the gate electrode having laterally opposite sidewalls that run perpendicular to the laterally opposite sidewalls of the semiconductor body, and wherein the gate electrode provides a first gate adjacent to the top surface of the semiconductor body, a second gate adjacent to one of the laterally opposite sidewalls of the semiconductor body, and a third gate adjacent to the other of the laterally opposite sidewalls of the semiconductor body;

forming a pair of sidewall spacers on the laterally opposite sidewalls of said gate electrode;

forming a semiconductor film on the top surface and on said laterally opposite sidewalls of said semiconductor body and adjacent to said sidewall spacer; and

forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

13. The method of claim 12 further comprising forming a halo region in said semiconductor body beneath said gate electrode.

14. The method of claim 12 wherein said gate electrode as a height of at least 3×

the height of said semiconductor body.

15. The method of claim 12 further comprising forming a refractory metal onto said semiconductor film on said top surface and said laterally opposite sidewalls of said semiconductor body.