Split gate flash memory cell and manufacturing method thereof

• US 7,358,134 B2
• Filed: 04/15/2005
• Issued: 04/15/2008
• Est. Priority Date: 09/15/2003
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Inventors: Huang, Tsai-Yu, Wu, Sheng
• Primary Examiner(s): Lindsay, Jr.; Walter
• Application Number:
  US10/907,781
• Publication Number:
  US 20060234444A1
• Time in Patent Office: 1,096 Days
• Field of Search: 438/257, 438/258, 438/259, 438/260, 438/261, 438/262, 438/263, 438/264, 438/265, 438/266, 438/267, 438/286, 257/E21.179
• US Class Current: 438/257
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A split gate flash memory cell includes a substrate having a device isolation structure; a selective gate structure disposed on the substrate; an interlayer dielectric layer having an opening disposed on the substrate, wherein the opening exposes a portion of the selective gate structure, the substrate and the device isolation structure; a floating gate disposed in the opening and extended to cover a surface of the interlayer dielectric layer; a tunneling dielectric layer disposed between the floating gate and the selective gate structure; a gate dielectric layer disposed between the floating gate and the control gate; a source region disposed in the substrate on one side of the control gate that is not adjacent to the selective gate structure, and a drain region disposed in the substrate on one side of the selective gate that is not adjacent to the control gate.

Claims

1. A fabrication method for a split gate flash memory cell, comprising:

providing a substrate, wherein the substrate is already formed with a device isolation structure;

forming a selective gate structure on the substrate, the selective gate structure comprises a gate dielectric layer, a conductive layer and a cap layer;

forming a spacer on a sidewall of the selective gate structure;

forming a source region and a drain region in the substrate beside both sides of the selective gate structure, wherein the source region is at a certain distance away from the selective gate structure, and the drain region is adjacent to the selective gate structure;

forming an interlayer dielectric layer on the substrate;

forming an opening in the interlayer dielectric layer, wherein the opening exposes the substrate between the selective gate structure and the source region, a portion of the selective gate structure and the device isolation structure;

forming a tunneling dielectric layer on the substrate that is exposed by the opening;

forming a floating gate in the opening, wherein the floating gate extends to a part of the interlayer dielectric layer;

forming a gate dielectric layer on the substrate; and

forming a control gate on the substrate, wherein the control gate fills the opening.

2. The method of claim 1, wherein the step of forming the control gate on the substrate further comprises:

forming a first conductive layer on the substrate, wherein the first conductive layer fills the opening; and

patterning the first conductive layer to form the control gate.

3. The method of claim 2, wherein the control gate covers the floating gate above the selective gate structure.

4. The method of claim 2, wherein the step of patterning the first conductive layer to form the control gate further comprises concurrently forming an erase gate on the substrate, wherein a portion of the erase gate covers the floating gate.

5. The method of claim 1, wherein forming the gate dielectric layer on the substrate further comprises:

forming a composite dielectric layer on the substrate;

patterning the composite dielectric layer, wherein only the composite dielectric layer disposed on a surface of the floating gate remains; and

forming a dielectric layer on the substrate.

6. The method of claim 5, wherein forming the composite dielectric layer on the substrate further comprises:

forming a first silicon oxide layer on the substrate using a thermal oxidation method;

forming a silicon nitride layer on the first silicon oxide layer using a chemical vapor deposition method; and

forming a second silicon oxide layer on the silicon nitride layer using a chemical vapor deposition method.

7. The method of claim 1, wherein forming the opening in the floating gate further comprises:

forming a second conductive layer on the substrate; and

patterning the second conductive layer to form the floating gate.

8. The method of claim 1, wherein forming the opening in the interlayer dielectric layer comprises:

forming a patterned photoresist layer on the substrate;

removing a portion of the interlayer dielectric layer to form the opening using the patterned photoresist layer, the cap layer and the spacer as a mask.

9. The method of claim 1, wherein subsequent to the step of forming the selective gate structure on the substrate, and before the step forming the spacer on the sidewall of the selective gate structure, the method further comprises forming a first lightly doped region and a second lightly doped region in the substrate beside both sides of the selective gate structure, wherein the first lightly doped region is at a certain distance away from the selective gate structure, and the second lightly doped region is adjacent to the selective gate structure.

10. The method of claim 1, wherein forming the spacer on the sidewall of the selective gate structure further comprises:

forming an insulating material on the substrate; and

performing an anisotropic etching process to remove a portion of the insulating material.