Wafer bonding of thinned electronic materials and circuits to high performance substrate

• US 7,358,152 B2
• Filed: 11/22/2005
• Issued: 04/15/2008
• Est. Priority Date: 07/12/2002
• Status: Expired due to Term

• Current Assignee: The Government Of The United States Of America, As Represented By The Secretary Of The Navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Hobart, Karl, Kub, Francis
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): Roman; Angel
• Application Number:
  US11/164,412
• Publication Number:
  US 20060199353A1
• Time in Patent Office: 875 Days
• Field of Search: 438/113, 438/114, 438/464, 438455-459, 257/E21.211
• US Class Current: 438/459
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 23/4827 Materials
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/10336 : Aluminium gallium arsenide [AlGaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.

Claims

1. A method of bonding a wafer to a substrate comprising the steps of:

providing a wafer having a front surface and a back surface;

attaching the front surface of the wafer to a support;

thinning the wafer from the back surface;

bonding the back surface of the wafer to a substrate by direct wafer bonding with atom-to-atom bonding; and

removing the support from the front surface of the wafer;

wherein the substrate has a resistivity higher than the resistivity of the wafer.

2. The method of claim 1, wherein the wafer comprises features on the front surface.

3. The method of claim 1, further comprising the step of:

processing the front surface to reduce stress in the front surface, before the attaching step.

4. The method of claim 3, wherein the processing step comprises forming grooves on the front surface of the wafer.

5. The method of claim 1, further comprising the step of:

applying a low stress material to the front surface, before the attaching step.

6. The method of claim 1, wherein the attaching step comprises the use of a material selected from the group consisting of a temporary adhesive, a dissolvable adhesive, an adhesive that melts, a releasable adhesive, a heat releasable adhesive, an ultraviolet releasable adhesive, a laser releasable adhesive, and a wax.

7. The method of claim 1, wherein:

the wafer comprises an etch stop layer; and

the thinning step comprises etching the back surface of the wafer.

8. The method of claim 1, wherein, the thinning step comprises grinding the back surface of the wafer.

9. The method of claim 7, further comprising the step of:

removing the etch stop layer after the thinning step and before the bonding step.

10. The method of claim 1, wherein the thinning step comprises thinning the wafer to a thickness of about 100 μ

m or less.

11. The method of claim 1, further comprising the step of:

reducing the surface roughness of the back surface of the wafer after the thinning step and before the bonding step.

12. The method of claim 11, wherein the step of reducing the surface roughness comprises polishing.

13. The method of claim 1, further comprising the step of:

forming features on the back surface of the wafer after the thinning step and before the bonding step.

14. The method of claim 1, further comprising the step of:

depositing a leakage current blocking insulator material layer onto the back surface of the wafer, the substrate, or both after the thinning step and before the bonding step.

15. The method of claim 1, further comprising the step of:

depositing a metallic layer onto the thinned back surface of the wafer, the substrate, or both before the bonding step.

16. The method of claim 1, wherein the substrate has a thermal conductivity higher than the thermal conductivity of the wafer.

17. The method of claim 1, wherein the substrate has a thermal conductivity of at least about 1 W/mK.

18. The method of claim 1, further comprising the step of:

cleaning the front surface of the wafer after the removing step.

19. The method of claim 1, further comprising the step of:

annealing the wafer bonded to the substrate after the bonding step and before the removing step.

20. The method of claim 1, further comprising the step of:

annealing the wafer bonded to the substrate after the removing step.

21. The method of claim 1, further comprising the step of:

forming features on the front surface of the wafer after the removing step.

22. The method of claim 1, further comprising the step of:

thinning the substrate after the bonding step.

23. The method of claim 22, wherein the step of thinning the substrate comprises thinning the substrate to a thickness of about 100 μ

m or less.

24. The method of claim 1, further comprising the step of:

cutting the substrate and bonded wafer.

25. The method of claim 1, wherein the bonding is carried out without a bonding material.