Architecture for face-to-face bonding between substrate and multiple daughter chips

• US 7,358,601 B1
• Filed: 06/29/2005
• Issued: 04/15/2008
• Est. Priority Date: 09/29/2004
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Plants, William C., Speers, Theodore, McCollum, John
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US11/171,488
• Time in Patent Office: 1,021 Days
• Field of Search: 257734-738, 257680-691, 257724-728, 257/777, 257/E21.006
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face thereof. Each member of the family of second integrated circuit dice have logical function circuits disposed thereon and further have a second array of face-to-face bonding structures disposed on a first face thereof. The second array of face-to-face bonding structures of each member of the family mates with a different portion of the first array of face-to-face bonding structures.

Claims

1. An integrated circuit system including:

a first integrated circuit die having input/output circuits disposed thereon and further having a first array of face-to-face bonding structures disposed on a first face thereof, the first integrated circuit die having no digital programmable logic circuits disposed thereon;

a family of second integrated circuit dice, each member of the family having digital programmable logic circuits disposed thereon and each member of the family having a size that is an integer multiple of a unit-tile size in each of an X and Y direction, further having a second array of face-to-face bonding structures disposed on a first face thereof, the second array of face-to-face bonding structures of each member of the family mates with different portion of the first array of face-to-face bonding structures, each member of the family having no input/output circuits disposed thereon.

2. The integrated circuit system of claim 1 wherein input/output circuits are disposed in a peripheral portion of the first integrated circuit die and the mating face-to-face bonding pads are disposed on the opposing face of the first integrated circuit die at an interior portion thereof.

3. The integrated circuit system of claim 1 wherein the digital programmable logic circuits on each member of the family of the second integrated circuit dice include a field programmable gate array having a different gate-count.

4. The integrated circuit system of claim 1 further including additional circuits disposed under the mating face-to-face bonding pads of the first integrated circuit die.

5. The integrated circuit system of claim 4 wherein the additional circuits include a digital-to-analog converter circuit.

6. The integrated circuit system of claim 4 wherein the additional circuits include an analog-to-digital converter circuit.

7. The integrated circuit system of claim 4 wherein the additional circuits include a voltage-regulator circuit.

8. The integrated circuit system of claim 4 wherein the additional circuits include a field-programmable-gate-array programming-control circuit.

9. The integrated circuit system of claim 4 wherein the additional circuits include at least one charge-pump circuit.

10. The integrated circuit system of claim 4 wherein the additional circuits include a data-conditioning circuit.

11. The integrated circuit system of claim 10 wherein the data-conditioning circuit comprises a serdes circuit.

12. The integrated circuit system of claim 11 wherein the data-conditioning circuit comprises a bus-interface circuit.

13. The integrated circuit system of claim 1 wherein the first array of face-to-face bonding structures is organized as a plurality of tiles and wherein the second array of face-to-face bonding structures of each member of the family of second integrated circuit dice is an integral number of the tiles.

14. An integrated circuit system comprising:

a mother integrated circuit die, including a substrate, input/output circuits disposed on the substrate, and an array of face-to-face bonding structures disposed on a surface of the substrate and organized into repeatable tiles, and adapted to receive a first daughter integrated circuit die and a second daughter integrated circuit die via face to face bonding at the array of bonding structures, the mother integrated circuit die having no digital programmable logic circuits disposed thereon; and

at least one first and second daughter integrated circuit dice including digital programmable logic circuits each connectable to the mother integrated circuit die via one of the tiles of bonding structures on the mother integrated circuit die, each at least one first and second daughter integrated circuit die having a size that is an integer multiple of a unit-tile size in each of an X and Y direction, and further having no input/output circuits disposed thereon.