Method and apparatus for PWM drive
First Claim
1. A method for driving a PWM motor drive, wherein a load is connected to output terminals of first and second output stage circuits, respectively, said output stage circuits driven by first and second PWM signals, respectively, each having a high level and a low level, from a PWM generating section, the method comprising:
- detecting a signal level of a first PWM signal;
determining whether one of first and second PWM signals is at low level or high level after the other of the first and second PWM signals is switched between a low level and a high level;
powering the load only when the first PWM signal and the second PWM signal are at different levels from each other;
providing dead time when two switching elements in series are both turned off, said switching elements constituting first and second output stage circuits, and thus operating the first and second output stage circuits; and
driving the load such that the first and second output stage circuits do not have dead time simultaneously.
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Abstract
During PWM control in which an actuator (9) is connected between the output terminals of a bridge circuit made up of switching elements (121, 122, 221, 222) and power is applied to the actuator (9) with signals G1U, G1L, G2U and G2L, driving timing signals are generated with a time interval (dead time) during which the switching elements (121, 122) and the switching elements (221, 222) are simultaneously turned off, and the actuator (9) is driven so as to have no overlapping dead time between a pair of half-bridge circuits, achieving response even with a differential input PWM signal (S51-S52) having a small time difference.
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Citations
5 Claims
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1. A method for driving a PWM motor drive, wherein a load is connected to output terminals of first and second output stage circuits, respectively, said output stage circuits driven by first and second PWM signals, respectively, each having a high level and a low level, from a PWM generating section, the method comprising:
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detecting a signal level of a first PWM signal; determining whether one of first and second PWM signals is at low level or high level after the other of the first and second PWM signals is switched between a low level and a high level; powering the load only when the first PWM signal and the second PWM signal are at different levels from each other; providing dead time when two switching elements in series are both turned off, said switching elements constituting first and second output stage circuits, and thus operating the first and second output stage circuits; and driving the load such that the first and second output stage circuits do not have dead time simultaneously.
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2. An apparatus for PWM drive, comprising:
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a PWM signal generating section for generating first and second PWM signals each having a pulse width determined by an analog input signal; a bridge circuit comprising first and second output stages each including two switching elements connected in series, the bridge circuit including a load connected between output terminals of the output stages; a first advanced edge decision section for deciding whether the first or second PWM signal is switched first and outputting a first advanced edge decision signal; a first timing pulse generating section for receiving the first PWM signal and the first advanced edge decision signal as input signals, and for having a dead time during which the switching elements connected in series and comprising the first output stage are simultaneously turned off, and for generating first and second driving timing signals causing no overlapping dead time between the first and second output stages; a second advanced edge decision section for deciding whether the first or second PWM signal is switched first and outputting a second advanced edge decision signal; and a second timing pulse generating section for receiving the second PWM signal and the second advanced edge decision signal as input signals, and for having a dead time during which the switching elements connected in series and comprising the second output stage are simultaneously turned off, and for generating third and fourth driving timing signals causing no overlapping dead time between the first and second output stages. - View Dependent Claims (3, 4, 5)
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Specification