Testing method and testing apparatus

• US 7,358,714 B2
• Filed: 01/19/2006
• Issued: 04/15/2008
• Est. Priority Date: 10/13/2005
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Watanabe, Takao, Ishihara, Shigenobu
• Primary Examiner(s): Nguyen; Ha Tran
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/334,399
• Publication Number:
  US 20070091698A1
• Time in Patent Office: 817 Days
• Field of Search: None
• US Class Current: 324/73.1
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A testing method of a semiconductor integrated circuit device includes a testing step of conducting a functional test by supplying test pattern data to a semiconductor integrated circuit device mounted upon a testing apparatus, and a post processing step conducted after the testing step for continuously driving the semiconductor integrated circuit device by supplying dummy test pattern to the semiconductor integrated circuit device, wherein the test pattern data is supplied with a first system clock speed while the dummy test pattern data is supplied with a second, slower system clock speed, the post processing step switching a system clock speed of the testing apparatus from the first system clock speed to the second system clock speed at the same time as finishing of the testing step.

Claims

1. A testing method of a semiconductor integrated circuit device, comprising;

a testing step of conducting a functional test by supplying test pattern data to a semiconductor integrated circuit device mounted upon a testing apparatus; and

a post processing step conducted after said testing step for continuously driving said semiconductor integrated circuit device after said testing step by supplying dummy test pattern to said semiconductor integrated circuit device,

wherein said test pattern data is supplied with a first system clock speed while said dummy test pattern data is supplied with a second, slower system clock speed,

said post processing step switching a system clock speed of said testing apparatus from said first system clock speed to said second system clock speed at the same time as finishing of said testing step.

2. The method as claimed in claim 1, wherein said second clock speed is decreased gradually in said post processing step.

3. The method as claimed in claim 2, wherein said post processing step decreases said clock speed by 50% per each clock pulse.

4. The testing method as claimed in claim 1, wherein said post processing step monitors a supply voltage supplied to said semiconductor integrated circuit device mounted upon said testing apparatus and determines said second system clock speed such that a voltage overshoot caused in said supply voltage does not exceed a predetermined level.

5. The testing method as claimed in claim 1, wherein said post processing step comprises the steps of:

monitoring a supply voltage supplied to said semiconductor integrated circuit device mounted upon said testing apparatus; and

connecting a capacitor element to a power supply unit provided in said testing apparatus, when said supply voltage has exceeded a predetermined level, for providing a supply voltage to said semiconductor integrated circuit device.

6. The method as claimed in claim 1, wherein said testing step comprises the steps of:

monitoring a supply voltage provided to said semiconductor integrated circuit device mounted upon said testing apparatus; and

connecting a charged capacitor element to a power supply unit providing said supply voltage to said semiconductor integrated circuit device mounted upon said testing apparatus when said supply voltage has decreased below a predetermined level.

7. A testing apparatus of semiconductor integrated circuit device, comprising:

a test bed mounted with a semiconductor device to be tested;

a power supply unit supplying a drive current to said semiconductor integrated circuit device mounted upon said test bed;

a pattern generator supplying test pattern data to said semiconductor integrated circuit device mounted upon said test bed; and

a verification circuit verifying a response of said semiconductor integrated circuit device caused in response to supply of said test pattern data,

wherein said testing apparatus further comprises a controller for controlling a system clock speed thereof,

said pattern generator supplying said test pattern data to said semiconductor integrated circuit device at the time of functional test of said semiconductor integrated circuit device, with a first system clock speed,

said pattern generator supplying dummy test pattern to said semiconductor integrated circuit device at the time of post processing conducted after said functional test with a second, slower system clock speed,

said controller changing a system clock speed of said testing apparatus from said first system clock speed to said second system clock speed at the same time to completion of said functional test.

8. The testing apparatus as claimed in claim 7, wherein said control unit decreases said second system clock speed gradually during said post processing.

9. The testing apparatus as claimed in claim 7, wherein said controller decreasing said second system clock speed by 50% per each clock pulse during said post processing.

10. The testing apparatus as claimed in claim 7, wherein said testing apparatus comprises a voltage monitor circuit monitoring a supply voltage provided to said semiconductor integrated circuit device mounted upon said monitoring apparatus, said controller determining said second clock speed such that a voltage surge caused in said supply voltage does not exceed a predetermined level.

11. The testing apparatus as claimed in claim 7, wherein said testing apparatus further comprises:

a voltage monitoring circuit monitoring a supply voltage provided to said semiconductor integrated circuit device mounted upon said testing apparatus; and

a capacitor element provided in a manner connectable to said power supply unit in parallel, said controller connecting said capacitor element to said power supply unit when said supply voltage has exceeded a predetermined level during said post processing.

12. The testing apparatus as claimed in claim 7, wherein said testing apparatus further comprises:

a voltage monitoring circuit monitoring a supply voltage provided to said semiconductor integrated circuit device mounted upon said testing apparatus; and

a capacitor element provided in a manner connectable to said power supply unit in parallel, said capacitor element being connected to a charging circuit, said controller connecting said capacitor element to said power supply unit when said supply voltage has exceeded a predetermined level during said post processing.