Voltage, temperature, and process independent programmable phase shift for PLL

• US 7,358,783 B1
• Filed: 03/25/2003
• Issued: 04/15/2008
• Est. Priority Date: 11/03/1998
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Kim, In Whan, Yeung, Wayne, Sung, Chiakang, Huang, Joseph, Wang, Xiaobao, Wang, Bonnie I., Nguyen, Khai
• Primary Examiner(s): Richards; N. Drew
• Assistant Examiner(s): Luu; An T.
• Application Number:
  US10/400,191
• Time in Patent Office: 1,848 Days
• Field of Search: 327/156, 327/159, 327/160, 331/17, 331/25
• US Class Current: 327/156
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03H 11/245 using field-effect transistor
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 2005/00045 Dc voltage control of a capacitor or of the coupling of a capacitor as a load
• CPC Class Codes: H03K 23/665 by presetting
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

Claims

1. A phase-locked loop circuit comprising:

a voltage controlled oscillator providing a VCO clock output;

a first counter having a first clock input coupled to the VCO clock output; and

a second counter having a second clock input coupled to the VCO clock output, wherein;

the second counter generates an output clock of the phase-locked loop circuit;

a phase difference between the output clock and an input clock is programmably selectable by storing a first initial value in a first memory of the second counter; and

a divider ratio of the second counter is stored in a second memory of the second counter.

2. The circuit of claim 1 wherein the first counter generates a feedback clock of the phase-locked loop circuit.

3. The circuit of claim 2 further comprising:

a phase detector circuit coupled to receive the feedback clock and the input clock of the phase-locked loop circuit.

4. The circuit of claim 1 further comprising:

a multiplexer coupled between the VCO clock output and the first counter.

5. The circuit of claim 1 wherein the first and second counters are down counters.

6. The circuit of claim 1 wherein the first counter and second counter are programmable frequency dividers.

7. The circuit of claim 1 wherein the first and second counters have asynchronous preset inputs.

8. A loop circuit comprising:

a feedback circuit receiving a reference clock signal and a feedback clock signal;

a chain of delay stages coupled to the feedback circuit, wherein a delay of the chain of delay stages is variable and at least one of the delay stages comprises bypass circuitry and buffer circuitry, further wherein an output of the bypass circuitry is coupled to an input of the buffer circuitry; and

enable circuitry with a first input coupled to a source of constant voltage, a second input coupled to an enable signal, and an output coupled to an input of a first delay stage, wherein applying a value to the enable signal holds all voltages in the chain of delay stages substantially constant until another value is applied to the enable signal.

9. The loop circuit of claim 8 wherein:

the enable circuitry comprises a multiplexer;

the first input is coupled to one data input of the multiplexer; and

the second input is coupled to a selector input of the multiplexer.

10. The loop circuit of claim 9 wherein another data input of the multiplexer is coupled to an output of a second delay stage.

11. The loop circuit of claim 8 wherein a third input of the enable circuitry is coupled to an output of a second delay stage.

12. The loop circuit of claim 8 wherein the delay stages are coupled together in a loop.

13. The loop circuit of claim 12 wherein at least one of the delay stages comprises an inverter.

14. The loop circuit of claim 8 wherein a first input of the bypass circuitry is coupled to an output of buffer circuitry of a first one of the delay stages.

15. The loop circuit of claim 14 further wherein a second input of the bypass circuitry is coupled to an output of buffer circuitry of a second one of the delay stages.

16. The loop circuit of claim 8 further comprising:

selection circuitry, wherein;

inputs of the selection circuitry are coupled to outputs of the delay stages; and

an output of the selection circuitry is coupled to the feedback clock signal.

17. The loop circuit of claim 16 wherein:

one of the delay stage outputs that is coupled to an input of the selection circuitry is also coupled to an output of the loop circuit without passing through the selection circuitry.

18. The loop circuit of claim 8 further comprising:

selection circuitry, wherein;

inputs of the selection circuitry are coupled to outputs of the delay stages; and

an output of the selection circuitry is coupled to an output of the loop circuit.

19. The loop circuit of claim 18 wherein:

one of the delay stage outputs that is coupled to an input of the selection circuitry is also coupled to the feedback clock signal without passing through the selection circuitry.