Reducing noise and/or power consumption in a switched capacitor amplifier sampling a reference voltage

• US 7,358,801 B2
• Filed: 08/05/2005
• Issued: 04/15/2008
• Est. Priority Date: 08/16/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ayyagari, Ravishankar S, Pentakota, Visvesvaraya A, Perdoor, Sandeep Mallya
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Flanagan; Krista M
• Application Number:
  US11/161,486
• Publication Number:
  US 20060033561A1
• Time in Patent Office: 984 Days
• Field of Search: None
• US Class Current: 330/9
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45973 by using a feedback circuit

Abstract

Equal common mode voltage is present at the input terminals of an operational amplifier with amplifies the residue signal in a stage of an ADC in two phases while reducing the noise introduced into the amplified signal. A reference capacitor is coupled between an input terminal of the operational amplifier and a reference voltage in a first phase, and between the input terminal and a the reference voltage but with opposite polarity in the second phase.

Claims

1. A switched capacitor amplifier circuit comprising:

an operational amplifier having a first input terminal and a second input terminal;

a first sampling capacitor being connected between an input signal and said first input terminal in a first phase; and

a first reference capacitor being coupled between said first input terminal and a reference voltage in said first phase, said first reference capacitor being connected between said first input terminal and a non-zero voltage in a second phase.

2. The switched capacitor amplifier circuit of claim 1, wherein said non-zero voltage represents said reference voltage but with opposite polarity.

3. The switched capacitor amplifier circuit of claim 2, further comprising:

a first feedback capacitor connected between said first input terminal and a first output terminal of said operational amplifier in said second phase,

wherein said first sampling capacitor is connected between a common mode reference voltage and said first input terminal in said second phase,

whereby the output (Vout) of said operational amplifier equals;

$\mathrm{Vout}=\frac{\mathrm{Cs}<br><br><br><br>1}{\mathrm{Cf}}\times <br><br>\left(\mathrm{Vinp}-\mathrm{Vcm}\right)-\frac{\mathrm{Cs}<br><br><br><br>2}{\mathrm{Cf}}<br><br>\left(V_{\mathrm{REF}}-V_1\right)$

wherein Cs1, Cs2 and Cf respectively represent the capacitance values of said first sampling capacitor, said first reference capacitor, and said first feedback capacitor, and Vinp, Vcm, Vref, and V1 respectively represent the voltage levels of said input signal, said common mode reference voltage, said reference voltage, and said non-zero voltage.

4. The switched capacitor amplifier circuit of claim 3, wherein Vcm is equal to 0 and V1 is equal to-Vref.

5. The switched capacitor amplifier circuit of claim 3, wherein said operational amplifier is operated in a differential mode, wherein Vref is equal to a difference between said reference voltage and said reference voltage with opposite polarity, V1 is equal to -Vref, and Vcm is equal to a common mode voltage of said input signal.

6. A device comprising:

a processor processing a plurality of digital values;

a switched capacitor amplifier circuit receiving an input signal and generating an amplified signal, each of said plurality of digital values being generated from said amplified signal, said switched capacitor amplifier circuit comprising;

an operational amplifier having a first input terminal and a second input terminal;

a first sampling capacitor being connected between an input signal and said first input terminal in a first phase; and

a first reference capacitor being coupled between said first input terminal and a reference voltage in said first phase, said first reference capacitor being connected between said first input terminal and a non-zero voltage in a second phase.

7. The device of claim 6, wherein said non-zero voltage represents said reference voltage but with opposite polarity.

8. The device of claim 7, further comprising:

a first feedback capacitor connected between said first input terminal and a first output terminal of said operational amplifier in said second phase,

wherein said first sampling capacitor is connected between a common mode reference voltage and said first input terminal in said second phase,

whereby the output (Vout) of said operational amplifier equals;

$\mathrm{Vout}=\frac{\mathrm{Cs}<br><br><br><br>1}{\mathrm{Cf}}\times <br><br>\left(\mathrm{Vinp}-\mathrm{Vcm}\right)-\frac{\mathrm{Cs}<br><br><br><br>2}{\mathrm{Cf}}<br><br>\left(\mathrm{VREF}-V<br><br><br><br>1\right)$

wherein Cs1, Cs2 and Cf respectively represent the capacitance values of said first sampling capacitor, said first reference capacitor, and said first feedback capacitor, and Vinp, Vcm, Vref, and V1 respectively represent the voltage levels of said input signal, said common mode reference voltage, said reference voltage, and said non-zero voltage.

9. The device of claim 8, wherein Vcm is equal to 0 and V1 is equal to -Vref.

10. The device of claim 8, wherein said operational amplifier is operated in a differential mode, wherein Vref is equal to a difference between said reference voltage and said reference voltage with opposite polarity, V1 is equal to -Vref, and Vcm is equal to a common mode voltage of said input signal.

11. The device of claim 6, wherein said switched capacitor amplifier circuit is comprised in a analog to digital converter (ADC).

12. The device of claim 11, further comprising:

a low noise amplifier receiving an external signal and generating an amplified signal;

a mixer down-converting said amplified signal using a carrier signal to generate a down-converted signal; and

a filter circuit filtering undesired components from said down-converted signal to generate said input signal;

wherein said ADC converts said input signal into said plurality of digital values.