Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers

• US 7,359,279 B2
• Filed: 03/31/2005
• Issued: 04/15/2008
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/095,415
• Publication Number:
  US 20060221752A1
• Time in Patent Office: 1,111 Days
• Field of Search: 365/51.X, 365/63.X, 365/230.03 X, 365/230.06 O, 365/51, 365/63, 365/230.03, 365/230.06
• US Class Current: 365/230.06
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

Claims

1. An integrated circuit comprising:

a memory array having a respective plurality of array lines of a first type for each of at least one memory layer;

a plurality of I/O bus lines;

a plurality of layer selector circuits, each responsive to an associated enable signal, for coupling respective array lines on an associated memory layer to respective ones of an associated group of said I/O bus lines, said plurality of layer selector circuits comprising;

layer selector circuits of a first type for coupling array lines on a first memory layer to a first group of said I/O bus lines;

layer selector circuits of a second type for coupling array lines on a second memory layer, if such second memory layer is present, to the first group of said I/O bus lines;

layer selector circuits of a third type for coupling array lines on the first memory layer to a second group of said I/O bus lines; and

layer selector circuits of a fourth type for coupling array lines on the second memory layer, if such second memory layer is present, to the second group of said I/O bus lines; and

control circuitry for selectively enabling certain layer selector circuits, said control circuitry configured, and said layer selector circuits arranged, to simultaneously couple a respective array line to each respective I/O bus line irrespective of whether the second memory layer is present.

2. The integrated circuit as recited in claim 1 wherein:

a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer, if such second memory layer is implemented, or otherwise coupled at such other times to an array line on the first memory layer.

3. The integrated circuit as recited in claim 1 wherein the control circuitry is configured by programming a configuration memory.

4. The integrated circuit as recited in claim 1 wherein the control circuitry is configured by the presence or absence of a feature on a layer associated with the second memory layer.

5. The integrated circuit as recited in claim 1 wherein:

the array lines of the first type comprise bit lines;

the memory array further comprises a plurality of word lines, each word line comprising a word line segment on each of one or more word line layers.

6. The integrated circuit as recited in claim 5 further comprising a word line decoder having a configuration that is independent of whether the second memory layer is implemented.

7. The integrated circuit as recited in claim 5 wherein the memory array comprises passive element memory cells.

8. The integrated circuit as recited in claim 7 comprising antifuse memory cells.

9. The integrated circuit as recited in claim 1 wherein:

the memory array is arranged in memory blocks; and

each memory block includes layer selector circuits of the first type and third type responsive to a single column select signal, and further includes layer selector circuits of the second type and fourth type responsive to a single column select signal.

10. The integrated circuit as recited in claim 1 wherein:

each respective layer selector circuit of the first type and each respective layer selector circuit of the third type share a respective one of a first group of enable signals;

each respective layer selector circuit of the second type and each respective layer selector circuit of the fourth type share a respective one of a second group of enable signals that are disabled if the second memory layer is not implemented.

11. The integrated circuit as recited in claim 10 wherein:

if the second memory layer is implemented, the first and second group of enable signals are responsive to an associated address, thereby coupling array lines on the first layer to both the first and second groups of I/O bus lines for half of the possible addresses, and coupling array lines on the second layer to both the first and second groups of I/O bus lines for the other half of the possible addresses; and

if the second memory layer is not implemented, the second group of enable signals are disabled, and the first group of enable signals are responsive to an associated address, thereby coupling array lines on the first layer to both the first and second groups of I/O bus lines for all available remaining addresses.

12. The integrated circuit as recited in claim 1 wherein:

the memory array is arranged in memory blocks; and

each memory block includes layer selector circuits of either the first type or the second type, but not both.

13. The integrated circuit as recited in claim 1 wherein:

each respective layer selector circuit of the first type and each respective layer selector circuit of the fourth type share a respective one of a first group of enable signals;

each respective layer selector circuit of the second type and each respective layer selector circuit of the third type share a respective one of a second group of enable signals.

14. The integrated circuit as recited in claim 13 wherein:

one enable signal is selected if the second memory layer is implemented, thereby coupling array lines on the first memory layer to the first group of I/O bus lines and coupling array lines on the second memory layer to the second group of I/O bus lines; and

one enable signal from each of the first and second groups is simultaneously selected if the second memory layer is not implemented, thereby coupling array lines on the first memory layer to the first group of I/O bus lines and coupling other array lines on the first memory layer to the second group of I/O bus lines.

15. The integrated circuit as recited in claim 13 wherein:

the pair of simultaneously selected enable signals fall within a single memory block.

16. The integrated circuit as recited in claim 13 wherein:

the pair of simultaneously selected enable signals fall respectively within adjacent memory blocks.

17. The integrated circuit as recited in claim 13 wherein:

the pair of simultaneously selected enable signals fall respectively within two non-adjacent memory blocks.

18. The integrated circuit as recited in claim 1 further comprising:

a second plurality of I/O bus lines on a side of the memory array opposite the aforementioned plurality of I/O bus lines;

a second plurality of layer selector circuits for both the first and second memory layers, each for coupling respective array lines on a memory layer to respective ones of the second plurality of I/O bus lines;

a second control circuit for enabling one or more of the second plurality of layer selector circuits, said second control circuit being configurable, and said second plurality of layer selector circuits being arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line of the second plurality irrespective of whether the second memory layer is implemented.

19. The integrated circuit as recited in claim 1 wherein:

the memory array is arranged in memory blocks;

each memory block that includes a layer selector circuit of the first type also includes a corresponding layer selector circuit of the fourth type, both responsive to the same enable signal; and

each memory block which includes a layer selector circuit of the second type also includes a corresponding layer selector circuit of the third type, both responsive to the same enable signal.

20. The integrated circuit as recited in claim 19 further comprising:

column selection circuits configured, in a memory array in which both first and second memory layers are implemented, for simultaneously selecting only one enable signal associated either with the first and fourth types of layer selector circuits or with the second and third types of layer selector circuits, and configured, in a memory array in which the second memory layer is not implemented, for simultaneously selecting two enable signals, one such enable signal associated with the first and fourth types of layer selector circuits and the other such enable signal associated with the second and third types of layer selector circuits.

21. The integrated circuit as recited in claim 19 wherein:

memory blocks of a first type include layer selector circuits of the first type and the fourth type; and

memory blocks of a second type include layer selector circuits of the second type and the third type.

22. The integrated circuit as recited in claim 21 wherein memory blocks of the first type alternate with memory blocks of the second type.

23. The integrated circuit as recited in claim 1 wherein:

each array selector circuit includes four coupling circuits, each coupling circuit responsive to a single colunm select signal, each for coupling an array line on a single memory layer to a respective one of a group of the I/O bus lines;

the plurality of I/O lines numbers sixteen; and

the memory array comprises a third memory layer configured analogously to the first memory layer.

24. A computer readable medium encoding an integrated circuit, said integrated circuit as recited in claim 1.

25. A integrated circuit comprising:

a memory array having at least one memory layer, each memory layer including a respective plurality of array lines of a first type;

means for configuring the memory array depending upon whether a second memory layer is present; and

means for coupling every respective one of a plurality of I/O bus lines for the memory array to a respective array line irrespective of whether the second memory layer is present, said means for coupling comprising;

layer selector circuits of a first type for coupling array lines on a first memory layer to a first group of said I/O bus lines;

layer selector circuits of a second type for coupling array lines on a second memory layer, if such second memory layer is present, to the first group of said I/O bus lines;

layer selector circuits of a third type for coupling array lines on the first memory layer to a second group of said I/O bus lines; and

layer selector circuits of a fourth type for coupling array lines on the second memory layer, if such second memory layer is present, to the second group of said I/O bus lines.

26. A method for use in an integrated circuit memory array having at least one memory layer, each memory layer including a respective plurality of array lines of a first type, said method comprising the steps of:

configuring the memory array depending upon whether a second memory layer is present;

coupling every respective one of a plurality of I/O bus lines for the memory array to a respective array line irrespective of whether the second memory layer is present;

wherein;

when a first signal is enabled, respectively coupling array lines from the first memory layer to respective I/O bus lines of a first group, and respectively coupling array lines from a second memory layer, if implemented, to respective I/O bus lines of a second group; and

when a second signal is enabled, respectively coupling array lines from the second memory layer, if implemented, to respective I/O bus lines of the first group, and respectively coupling array lines from the first memory layer to respective I/O bus lines of the second group.

27. The method as recited in claim 26 wherein the configuring step comprises sensing the presence or absence of a feature on a layer associated with the second memory layer.

28. The method as recited in claim 26 wherein the configuring step comprises programming a configuration memory.

29. The method as recited in claim 26 wherein:

a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer, if such second memory layer is implemented, or otherwise coupled at such other times to an array line on the first memory layer.

30. The method as recited in claim 26 wherein:

the first signal comprises a first column select signal, and the second signal comprises a second column select signal.

31. The method as recited in claim 30 further comprising:

individually enabling the first and second column select signals in a memory array in which both memory layers are implemented; and

simultaneously enabling the first and second column select signals in a memory array in which only the first memory layer is implemented.

32. The method as recited in claim 31 wherein the simultaneously enabled first and second column select signals are associated with a single memory block.

33. The method as recited in claim 31 wherein the simultaneously enabled first and second column select signals are associated with adjacent memory blocks.

34. The method as recited in claim 31 wherein the simultaneously enabled first and second colunn select signals are associated with two non-adjacent memory blocks.

35. The method as recited in claim 26 wherein:

when a first select signal is enabled, respectively coupling array lines from the first memory layer to respective I/O bus lines of a first group and of a second group; and

when a second select signal is enabled, respectively coupling array lines from the second memory layer, if implemented, to respective I/O bus lines of the first group and of the second group.