Robust calculation of crosstalk delay change in integrated circuit design

• US 7,359,843 B1
• Filed: 12/12/2003
• Issued: 04/15/2008
• Est. Priority Date: 09/19/2003
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Keller, Igor, Verghese, Nishath, Tseng, Kenneth
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US10/735,123
• Time in Patent Office: 1,586 Days
• Field of Search: 703/19, 703/13, 703/2, 716/6
• US Class Current: 703/2
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method of delay change determination in an integrated circuit design including a stage with a victim net and one or more aggressor nets capacitively coupled thereto, the method comprising: determining a nominal (noiseless) victim net signal transition; determining a noisy victim net signal transition; and determining a delay change based upon nominal and noisy victim signal transition arrival times at a victim net receiver output.

Claims

1. A computer implemented method of determining aggressor-induced delay change in a victim net of a stage of an integrated circuit design, the stage including a victim net driver gate, a receiver gate and an interconnect network including a victim net and an aggressor net, comprising:

providing an input and output voltage dependent current model of the victim net driver gate;

producing a model of a load presented to an output of the driver gate by the interconnect network;

producing a model of the interconnect network of the stage, which can be used to propagate a waveform from an output of the driver gate to an input of the receiver gate;

simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,

providing a signal transition at an input of the driver gate;

using the current model of the driver gate and the load model of the interconnect network to produce a nominal driver gate output waveform resulting from the provided input signal transition; and

using the interconnect model to propagate the nominal driver gate output waveform from the driver gate output to the receiver gate input;

simulating behavior of the victim net during noisy transition by performing steps including,

providing a signal transition at an input of the driver gate;

providing an aggressor-induced current waveform to an output of the driver gate;

using the current model of the driver gate and the load model of the interconnect network to produce a noisy driver gate output waveform resulting from the provided input signal transition and the aggressor-induced current waveform; and

using the interconnect model to propagate the noisy driver gate output waveform from the driver gate output to the receiver gate input;

providing an aggressor-induced voltage waveform to an input of the receiver gate;

producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition; and

saving the produced value in computer readable memory.

2. The method of claim 1,

wherein the output current-dependent model of a driver of the victim net includes a ViVo model.

3. The method of claim 1,

wherein the output current-dependent model of a driver of the victim net includes a ViVo model;

and

wherein the load model includes a Ø

-load model.

4. The method of claim 1 further including,

providing an input and output voltage dependent current model of the receiver gate;

wherein simulating behavior of the victim net during nominal transition further includes using at least the receiver gate current model to produce a nominal receiver gate output waveform resulting from the propagated nominal driver gate; and

wherein simulating behavior of the victim net during noisy transition further includes using at least the receiver gate current model to produce a noisy receiver gate output waveform resulting from the propagated noisy driver gate output waveform and the at least one aggressor-induced voltage waveform provided to the receiver model input.

5. The method of claim 1,

wherein simulating behavior of the victim net during nominal (noiseless) transition further includes,

using a current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated nominal driver gate output waveform;

and

wherein simulating behavior of the victim net during noisy transition further includes, using the current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated noisy driver gate output waveform and the aggressor-induced voltage waveform to an input of the receiver gate.

6. The method of claim 1 further including:

precomputing the current waveform through a driver gate pin induced by a transitioning aggressor net to produce the aggressor-induced current waveform; and

precomputing the voltage waveform at a receiver pin induced by the transitioning aggressor net to produce the aggressor-induced voltage waveform.

7. The method of claim 1,

wherein providing a model of the interconnect network includes providing a computational model that includes a transfer function that includes an admittance matrix that relates voltage on one port of the matrix to current on another port of the matrix;

using the computational model to compute the aggressor-induced current waveform; and

using the computational model to compute the aggressor-induced voltage waveform.

8. The method of claim 1,

wherein the load model approximates output point admittance of the interconnect network.

9. The method of claim 1,

wherein the model of the load represents a Π

-load model and further includes a model of capacitance of the driver gate output pin.

10. An article of manufacture including a computer readable medium encoded with an information structure representing a driver circuit, the information structure comprising:

a current model that associates instantaneous values of input node voltage, output node voltage and output node current of the driver circuit;

a model of capacitance between an input node and an output node of the driver circuit; and

a model of capacitance between the output node of the driver circuit and a ground potential;

wherein the information structure is operable to cause a computer to associate current drawn by the driver circuit output node in response to voltages applied to the driver circuit input and output nodes.

11. The article of manufacture of claim 10 wherein,

the driver circuit includes multiple channel connected cells;

and

the driver circuit current model includes a model of a last channel connected component of the driver circuit.

12. The article of manufacture of claim 10 wherein,

the driver circuit includes multiple channel connected cells;

and

the driver circuit current model includes a model of only a last channel connected component of the driver circuit.

13. The article of manufacture of claim 10,

wherein the driver circuit includes multiple channel connected cells;

and

wherein the driver circuit current model includes a model of a last at least one channel connected component of the driver circuit; and

further including;

information concerning slew on the input node of the at least one component characterized as a function of slew on at least one input node of the driver.

14. The article of manufacture of claim 10,

wherein the driver circuit includes multiple channel connected cells;

and

wherein the driver circuit current model includes a model of only a last channel connected component of the driver circuit; and

further including;

information concerning slew on the input node of the at least one component characterized as a function of slew on at least one input node of the driver.

15. An article of manufacture including a computer readable medium encoded with an information structure representing a driver circuit, the information structure comprising:

a current model that associates instantaneous values of driver circuit input node voltage, driver circuit output node voltage and driver circuit output node current;

a model of miller capacitance of the output node of the driver circuit; and

a model of ground capacitance of the output node of the driver circuit;

wherein the information structure is operable to cause a computer to associate current drawn by the driver circuit output node in response to voltages applied to the driver circuit input and output nodes.

16. The article of manufacture of claim 15,

wherein the driver circuit includes multiple channel connected cells;

and

wherein the driver circuit current model includes a model of only a last channel connected component of the driver circuit; and

further including;

information concerning slew on the input node of the at least one component characterized as a function of slew on at least one input node of the driver.

17. An article of manufacture including a computer readable medium encoded with computer instructions to cause the computer to perform a circuit simulation process comprising the steps of:

for each of a plurality of different pairs of first and second DC voltage values,

sensitizing an input node of a cell model of the driver circuit with a first DC voltage value;

sensitizing an output node of the cell model with a second DC voltage value;

generating a value of current drawn by the output node of the cell model based upon the provided first DC voltage value and the provided second DC voltage value; and

saving the generated value in computer readable memory.

18. The article of manufacture of claim 17, the process further including:

producing a table representing respective associations among respective pairs of first DC voltage values and second DC voltage values and respective current values generated based upon such respective pairs.

19. The article of manufacture of claim 17 wherein,

each respective first DC value includes a constant DC value;

and

each respective second DC value includes a constant DC value.

20. The article of manufacture of claim 17 wherein,

the driver circuit model includes a model of at least one channel connected component of the driver circuit.

21. The article of manufacture of claim 17 wherein,

the driver circuit model includes a model of a last channel connected component of the driver.

22. The article of manufacture of claim 17 wherein,

the driver circuit model includes a model of only a last channel connected component of the driver.

23. The article of manufacture of claim 17, the process further including:

producing a model of capacitance between the input node and the output node of the driver circuit; and

producing a model of capacitance between the output node of the driver circuit and a ground potential.

24. The article of manufacture of claim 17, the process further including:

determining capacitance between the input node and the output node of the driver circuit through transient analysis; and

determining capacitance between the output node the driver circuit and a ground potential through transient analysis.

25. The article of manufacture of claim 17,

wherein the driver circuit includes multiple channel connected cells;

and

wherein the driver circuit model includes a model of only a last channel connected component of the driver;

the process further including;

determining a slew on an input node of the cell model of the driver circuit characterized as a function of slew on an input node of the cell model of the driver circuit.

26. The article of manufacture of claim 17,

wherein the driver circuit model includes only a model of a last channel connected component of the driver;

further including;

determining a slew on an input node of the cell model characterized as a function of slew on an input node of the cell model of the driver circuit.

27. An article of manufacture including a computer readable medium encoded with a current model of a driver circuit, the current model operable to cause the computer to associate input voltage values, output voltage values and current values, the current model produced by a process including the steps of:

for each of a plurality of different pairs of first and second DC voltage values,

sensitizing an input node of a cell model representing the driver circuit with a first DC voltage value;

sensitizing an output node of the cell model with a second DC voltage value; and

generating a value of current drawn by the output node of the cell model based upon the provided first DC voltage value and the provided second DC voltage value.

28. The article of claim 27 wherein the process further includes the step of:

producing a table representing the respective associations among first DC voltage values, second DC voltage values and current values.

29. The article of claim 27 wherein,

each respective first DC value includes a constant DC value;

and

each respective second DC value includes a constant DC value.

30. An article of manufacture including a computer readable medium encoded with instructions to cause the computer to perform a method of simulating aggressor-induced behavior of a driver circuit and an interconnect network driven by the driver circuit, the method comprising:

providing a voltage signal transition on an input of a current model representing the driver circuit, the current model associating instantaneous values of input voltage, output voltage and output current of the driver circuit;

providing an aggressor induced current waveform on a node interconnecting an output of the current model and a load model representing the interconnect network, the load model approximating output point admittance of the interconnect network; and

using the current model and the load model to produce a voltage waveform on the output of the current model based upon the received input voltage signal transition and the received aggressor induced waveform;

wherein the voltage waveform represents a voltage transition on the driver circuit output.

31. The article of manufacture of claim 30,

wherein the current model includes a model of capacitance associated with the driver circuit.

32. The article of manufacture of claim 30,

wherein the current model includes a model of miller capacitance associated with the driver circuit;

and

wherein the current model includes a model of ground capacitance associated with the driver circuit.

33. The article of manufacture of claim 30 wherein,

the load model includes a Π

-model.

34. The article of manufacture of claim 30 wherein,

the at least one component comprises a channel connected component.

35. The article of manufacture of claim 30 wherein,

the current model includes a model of a last channel connected component of the driver.

36. A computer implemented method of determining aggressor-induced delay change in a victim net in an integrated circuit design, the victim net including a driver circuit and an interconnect network between the driver circuit and a receiver circuit, the method comprising:

simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,

providing a voltage signal transition on an input of the driver circuit;

using a driver circuit current model and a load model approximating output point admittance of the interconnect network presented to an output of the driver circuit, to produce a nominal driver circuit output voltage waveform resulting from the provided transition signal; and

using a computational model of the interconnect network to propagate the nominal driver circuit output voltage waveform to an input of the receiver circuit;

simulating behavior of the victim net during noisy transition by performing steps including,

providing a voltage signal transition on the input of the driver circuit;

providing an aggressor induced current waveform to the output node of the driver circuit;

using the driver circuit current model and the load model to produce a noisy driver circuit output voltage waveform resulting from the provided transition signal and the aggressor-induced current waveform; and

using the computational model of the interconnect network to propagate the noisy output voltage waveform to an input of the receiver circuit;

producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition; and

saving the produced value in computer readable memory.

37. The method of claim 36,

wherein the current model includes a model of capacitance of the driver circuit.

38. The method of claim 36,

wherein the current model includes a model of miller capacitance of the driver circuit;

and

wherein the current model includes a model of gate capacitance of the driver circuit.

39. The method of claim 36 wherein,

the load model includes a Π

-model.

40. The method of claim 36 wherein,

the current model includes a model of a last channel connected component of the driver circuit.

41. The method of claim 36 wherein,

the computational model of the interconnect network includes one or more transfer functions that relate a signal on a driver circuit output node to a signal on a receiver circuit input node.

42. The method of claim 36 wherein,

the model of the receiver includes a current model.

43. The method of claim 36 wherein,

the driver circuit current model associates instantaneous values of input node voltage, output node voltage and output node current of the driver circuit.

44. The method of claim 36 wherein,

the driver circuit current model associates instantaneous values of input node voltage, output node voltage and output node current of the driver circuit;

and

the driver circuit current model includes a model of capacitance between an input node and an output node of the driver circuit; and

the driver circuit current model includes a model of capacitance between the output node of the driver circuit and a ground potential.

45. The method of claim 36,

wherein simulating behavior of the victim net during nominal transition further includes,

using a receiver circuit current model of the receiver circuit to produce a receiver circuit nominal output waveform, resulting from the propagated nominal output voltage waveform;

and

wherein simulating behavior of the victim net during noisy transition further includes,

using the receiver circuit current model to produce a receiver circuit noisy output waveform, resulting from the propagated noisy output voltage waveform.

46. The method of claim 36,

wherein simulating behavior of the victim net during nominal transition further includes,

using a receiver circuit current model of the receiver circuit to produce a receiver circuit nominal output waveform, resulting from the propagated nominal output voltage waveform;

and

wherein simulating behavior of the victim net during noisy transition further includes,

providing an aggressor-induced voltage waveform at an input of the receiver circuit; and

using the receiver circuit current model to produce a receiver circuit noisy output waveform, resulting from the propagated noisy output voltage waveform and the aggressor-induced voltage waveform at an input of the receiver circuit.

47. An article of manufacture including a computer readable medium encoded with instructions to cause the computer to perform a method of determining aggressor-induced delay change in a victim net of a stage of an integrated circuit design, the stage including a victim net driver gate, a receiver gate and an interconnect network including a victim net and an aggressor net, the method comprising:

simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,

providing a signal transition to an input of the driver gate;

using a current model of the driver gate and a load model of the interconnect network to produce a nominal driver gate output waveform resulting from the provided input signal transition; and

using a model of the interconnect network to propagate the nominal driver gate output waveform from the driver gate output to the receiver gate input;

simulating behavior of the victim net during noisy transition by performing steps including,

providing a signal transition at the input of the driver gate;

providing at least one aggressor-induced current waveform to an output of the driver gate;

using the current model of the driver gate and the load model of the interconnect network to produce a noisy driver gate output waveform resulting from the provided input signal transition and the at least one aggressor-induced current waveform provided to the driver gate output; and

using the interconnect model to propagate the noisy driver gate output waveform from the driver gate output to the receiver gate input;

providing at least one aggressor-induced voltage waveform to an input of the receiver gate;

producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition; and

saving the produced value to computer readable memory.

48. The article of claim 47, wherein the method further including:

providing as the current model, an input and output voltage dependent current model of the driver gate;

producing as the load model, a model of a load presented to an output of the driver gate by the interconnect network; and

producing as the model of the interconnect network, a computational model of the interconnect network that includes one or more transfer functions that relate a signal on a driver gate output node to a signal on a receiver gate input node.

49. The article of claim 47,

wherein simulating behavior of the victim net during nominal (noiseless) transition further includes,

using a current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated nominal driver gate output waveform;

and

wherein simulating behavior of the victim net during noisy transition further includes,

using the current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated noisy driver gate output waveform.

50. The article of claim 47,

wherein simulating behavior of the victim net during nominal (noiseless) transition further includes,

using a current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated nominal driver gate output waveform;

and

wherein simulating behavior of the victim net during noisy transition further includes,

providing an aggressor-induced voltage waveform at an input of the receiver gate; and

using the current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated noisy driver gate output waveform and the aggressor-induced voltage waveform at an input of the receiver gate.

51. An article of manufacture including a computer readable medium encoded with instructions to cause the computer to perform a method of determining aggressor-induced delay change in a victim net of a stage of an integrated circuit design, the stage including a victim net driver gate, a receiver gate and an interconnect network including the victim net and an aggressor net, the method comprising:

simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,

providing a voltage signal transition on an input of a the driver gate;

using a current model of the driver gate and a load model representing the interconnect network, the load model approximating output point admittance of the interconnect network, to produce a nominal driver gate output voltage waveform in response to the input voltage transition; and

using a computational model of the interconnect network to propagate the nominal driver gate output voltage waveform to an input of the receiver gate;

simulating behavior of the victim net during noisy transition by performing steps including,

providing a voltage signal transition to the input of the driver gate;

providing an aggressor induced current waveform to an output of the driver gate;

using the current model of the driver gate and the load model to produce a noisy driver gate output voltage waveform in response to the input voltage transition and the aggressor induced current waveform; and

using the computational model of the interconnect network to propagate the noisy driver gate output voltage waveform to an input of the receiver gate;

producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition; and

saving the produced value to computer readable memory.

52. The article of manufacture of claim 51,

wherein simulating behavior of the victim net during nominal (noiseless) transition further includes,

using a current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated nominal driver gate output waveform;

and

wherein simulating behavior of the victim net during noisy transition further includes,

using the current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated noisy driver gate output waveform.

53. The article of manufacture of claim 51,

wherein simulating behavior of the victim net during nominal (noiseless) transition further includes,

using a current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated nominal driver gate output waveform;

and

wherein simulating behavior of the victim net during noisy transition further includes,

providing an aggressor-induced voltage waveform at an input of the receiver gate; and

using the current model of the receiver gate to produce a receiver gate output waveform resulting from the propagated noisy driver gate output waveform and the aggressor-induced voltage waveform at an input of the receiver gate.

54. The article of manufacture of claim 51 wherein the information structure further includes:

a model of a load presented by an interconnect network associated with an output of the driver model.

55. The article of manufacture of claim 54,

wherein the load model approximates output point admittance of the interconnect network.

56. The article of manufacture of claim 54,

wherein the model of the load includes a Π

-model.