Synchronizing an instruction cache and a data cache on demand

• US 7,360,022 B2
• Filed: 12/29/2005
• Issued: 04/15/2008
• Est. Priority Date: 12/29/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Tian, Kun, Dong, Yaozu
• Primary Examiner(s): Verbrugge; Kevin
• Application Number:
  US11/322,008
• Publication Number:
  US 20070156969A1
• Time in Patent Office: 838 Days
• Field of Search: None
• US Class Current: 711/123
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches

Abstract

In one embodiment, the present invention includes a method for performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache, and synchronizing the page in the data cache and an instruction cache if the page implicates instruction information, otherwise not synchronizing the page. In this manner, synchronizations may be performed on demand. Other embodiments are described and claimed.

Claims

1. A method comprising:

performing a direct memory access (DMA) operation in a virtualized environment to obtain a page from a memory and store the page in a data cache; and

synchronizing the page in the data cache and an instruction cache if the page implicates instruction information, otherwise not synchronizing the page.

2. The method of claim 1, further comprising determining whether the page implicates the instruction information.

3. The method of claim 2, wherein determining whether the page implicates the instruction information comprises checking whether the page is mapped with an instruction translation by a guest software.

4. The method of claim 3, wherein checking whether the page is mapped comprises accessing a first indicator of an entry of a shared buffer, the entry corresponding to the page.

5. The method of claim 2, wherein determining whether the page implicates the instruction information comprises receiving an instruction translation lookaside buffer (I-TLB) insertion operation for the page from a guest software.

6. The method of claim 5, further comprising determining if the page is synchronized in the data cache and the instruction cache after receiving the I-TLB insertion operation by accessing a second indicator of an entry of a shared buffer, the entry corresponding to the page.

7. The method of claim 6, further comprising synchronizing the page in the data cache and the instruction cache if the page is determined not to be synchronized.

8. The method of claim 5, further comprising writing a first indicator in an entry of a shared buffer corresponding to the page after receiving the I-TLB insertion operation.

9. An article comprising a machine-accessible medium including instructions that when executed cause a system to:

read a page of information from a storage medium into a data cache;

determine if the page is for code execution; and

synchronize the page in the data cache and an instruction cache if the page is for code execution, otherwise to not synchronize the page.

10. The article of claim 9, further comprising instructions that when executed cause the system to access a first flag in an entry of a shared buffer corresponding to the page and to synchronize the page based on the first flag.

11. The article of claim 10, further comprising instructions that when executed cause the system to write a second flag in the entry if the page is not synchronized.

12. The article of claim 9, further comprising instructions that when executed cause the system to access a second flag in an entry of a shared buffer corresponding to the page and to synchronize the page based on the second flag, if the page is subjected to an instruction-translation lookaside buffer insertion operation.

13. The article of claim 12, further comprising instructions that when executed cause the system to write a first flag and to update the second flag in the entry after the synchronization.

14. An apparatus comprising:

an instruction cache to store pages including code;

a data cache to store pages including data; and

a shared buffer coupled to the instruction cache and the data cache, the shared buffer including entries each corresponding to one of a plurality of pages in a storage medium coupled to at least the data cache, wherein each of the entries includes status information regarding a synchronization state of the corresponding page in the instruction cache and the data cache.

15. The apparatus of claim 14, further comprising a first synchronizer to execute in a virtual machine monitor (VMM), the first synchronizer to synchronize a page in the instruction cache and the data cache based on the synchronization state of the page.

16. The apparatus of claim 15, wherein each of the entries further includes status information regarding a code mapping status of the corresponding page in the data cache.

17. The apparatus of claim 16, further comprising a second synchronizer to execute in a driver virtual machine (VM), the second synchronizer to synchronize a page in the instruction cache and the data cache based on the code mapping status of the page.

18. A system comprising:

an instruction cache to store instruction information;

a data cache coupled to the instruction cache to store data; and

a synchronizer coupled to the instruction cache and the data cache to synchronize a page in the instruction cache and the data cache if the page implicates instruction information, wherein the synchronizer is to not synchronize the page if the page is for data only.

19. The system of claim 18, further comprising:

a storage medium coupled to the data cache, wherein the storage medium is to store a plurality of pages; and

a shared buffer coupled to the synchronizer, the shared buffer to store a plurality of entries each corresponding to one of the plurality of pages of the storage medium.

20. The system of claim 19, wherein each of the plurality of entries includes a first indicator indicative of a mapping status of the corresponding page and a second indicator indicative of a synchronization status of the corresponding page.

21. The system of claim 20, wherein the synchronizer includes:

a first synchronizer to execute in a driver virtual machine (VM), the first synchronizer to determine whether to synchronize the corresponding page based on the first indicator; and

a second synchronizer to execute in a virtual machine monitor (VMM), the second synchronizer to determine whether to synchronize the corresponding page based on the second indicator.

22. The system of claim 21, wherein the first synchronizer is to write to the second indicator when the driver VM performs a direct memory access (DMA) operation for the corresponding page and the first indicator is indicative of the corresponding page being code mapped.

23. The system of claim 22, further comprising a device model to perform the DMA operation in the driver VM to read the corresponding page from the storage medium to the data cache.

24. The system of claim 21, wherein the second synchronizer is to write to the first indicator when a guest software issues an instruction translation lookaside buffer (TLB) insertion operation for the corresponding page.