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Integrated circuit memory device having delayed write capability

DC CAFC
  • US 7,360,050 B2
  • Filed: 03/02/2007
  • Issued: 04/15/2008
  • Est. Priority Date: 10/10/1997
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit memory device comprising:

  • a memory core including a plurality of memory cells;

    a first set of pins to receive, using a clock signal, a row address, followed by a column address;

    a second set of pins to receive, using the clock signal;

    a sense command, the sense command to specify that the memory device activate a row of memory cells of the plurality of memory cells identified by the row address, anda write command during a first time period, the write command to specify that the memory device receive write data and store the write data at a location in the row of memory cells, the location identified by the column address, wherein the write command is posted internally to the memory device after a first delay has transpired from the first time period; and

    a third set of pins to receive the write data after a second delay has transpired from the first time period.

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