Integrated circuit memory device having delayed write capability
DC CAFCFirst Claim
1. An integrated circuit memory device comprising:
- a memory core including a plurality of memory cells;
a first set of pins to receive, using a clock signal, a row address, followed by a column address;
a second set of pins to receive, using the clock signal;
a sense command, the sense command to specify that the memory device activate a row of memory cells of the plurality of memory cells identified by the row address, anda write command during a first time period, the write command to specify that the memory device receive write data and store the write data at a location in the row of memory cells, the location identified by the column address, wherein the write command is posted internally to the memory device after a first delay has transpired from the first time period; and
a third set of pins to receive the write data after a second delay has transpired from the first time period.
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Abstract
An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.
146 Citations
31 Claims
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1. An integrated circuit memory device comprising:
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a memory core including a plurality of memory cells; a first set of pins to receive, using a clock signal, a row address, followed by a column address; a second set of pins to receive, using the clock signal; a sense command, the sense command to specify that the memory device activate a row of memory cells of the plurality of memory cells identified by the row address, and a write command during a first time period, the write command to specify that the memory device receive write data and store the write data at a location in the row of memory cells, the location identified by the column address, wherein the write command is posted internally to the memory device after a first delay has transpired from the first time period; and a third set of pins to receive the write data after a second delay has transpired from the first time period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit memory device comprising:
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a memory core including a plurality of memory cells; a command interface to receive, using a clock signal, an activate command, a row address, a first bank address associated with the activate command, a write command, a column address, and a second bank address associated with the write command, wherein; the activate command specifies that the memory device activate a row of memory cells identified by the row address, located in a bank of the memory cells identified by the first bank address, and the write command specifies that the memory device receive write data to be stored to a location in the row of memory cells in a bank identified by the second bank address, wherein the location is identified by the column address; a data interface to receive the write data after a first delay has transpired from when the write command is received at the command interface; and a circuit to cause a second delay, after the write command is received at the command interface, when issuing control information internally to the integrated circuit memory device in response to the write command. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method of operation of an integrated circuit memory device that includes a memory core having a plurality of memory cells:
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receiving, using a clock signal, a row address, followed by a column address at a first set of pins; receiving, using the clock signal, a sense command at a second set of pins, wherein the sense command specifies that the memory device activate a row of memory cells of the plurality of memory cells identified by the row address; receiving, using the clock signal, a write command at the second set of pins, wherein the write command specifies that the memory device receive write data and store the write data at a column of the row of memory cells, the column identified by the column address; presenting the write command internally after a first delay has transpired from receiving the write command; and receiving at a third set of pins, after a second delay has transpired from receiving the write command, two consecutive bits of write data for every pin of the third set of pins, during a clock cycle of the clock signal. - View Dependent Claims (20, 21)
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22. A method of operation of an integrated circuit memory device having a memory core including a plurality of memory cells, the method comprising:
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receiving, using a clock signal, a row address that identifies a row of memory cells of the plurality of memory cells; receiving, using the clock signal, a first bank address that identifies a bank of the memory core that contains the row; receiving, using the clock signal, a column address that identifies a location in the row of memory cells; receiving, using the clock signal, a second bank address that identifies a bank of the memory core that contains the location; receiving, using the clock signal, a sense command and a write command, wherein; the sense command specifies that the memory device activate the row identified by the row address and the first bank address, and the write command specifies that the memory device receive write data and store the write data to the location identified by the column address and the second bank address; and receiving at a first set of pins, after a first delay has transpired from receiving the write command, two consecutive bits of the write data for every pin of the first set of pins, during a clock cycle of the clock signal. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A method of operating an integrated circuit memory device that receives a clock signal and includes a memory core having a plurality of banks, the method comprising:
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providing a sense command to a command interface of the memory device, wherein the sense command specifies that the memory device activate a row of memory cells in a bank identified by a first bank address; providing a row address that identifies the row of memory cells in the bank identified by the first bank address; providing a column address that identifies a location within the row of memory cells in a bank identified by a second bank address; providing a write command to the command interface of the memory device after providing the sense command, wherein the write command specifies that the memory device receive write data and store the write data in the location within the row of memory cells, wherein the write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the command interface of the memory device; and providing to a data interface of the memory device, at least two consecutive bits of write data during a clock cycle of the clock signals, after a second delay has transpired after providing the write command. - View Dependent Claims (30, 31)
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Specification