Second stage SOVA detector

• US 7,360,147 B2
• Filed: 05/18/2005
• Issued: 04/15/2008
• Est. Priority Date: 05/18/2005
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Vasiliev, Peter Igorevich
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US11/131,797
• Publication Number:
  US 20060282753A1
• Time in Patent Office: 1,063 Days
• Field of Search: 714/794, 714/796, 704/242, 375/262
• US Class Current: 714/794
• CPC Class Codes: H03M 13/4146 soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
• CPC Class Codes: H03M 13/4153 two-step SOVA decoding, i.e. the soft-output is determined by a second traceback operation after the determination of the hard decision like in the Berrou decoder
• CPC Class Codes: H03M 13/4184 using register-exchange H03M13/4192 takes precedence
• CPC Class Codes: H03M 13/6331 Error control coding in combination with equalisation

Abstract

A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.

Claims

1. A second stage SOVA detector, comprising:

a dynamic state reordering block that has inputs for receiving absolute state domain data and that provides relative state domain data and selection bit outputs;

pipeline registers receiving the relative state domain data outputs and the selection bit outputs and providing pipelined outputs; and

a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.

2. The second stage SOVA detector of claim 1 wherein the detected data bits and the reliabilities form a signed numerical value, and the sign represents the data and the numerical value represents the reliability.

3. The second stage SOVA detector of claim 1 wherein the detected data bits comprise read channel data from a data storage device.

4. The second stage SOVA detector of claim 1 wherein the dynamic state reordering block maintains values of current state of maximum likelihood path and the maximum likelihood competitive path in the relative state domain data and selection bit outputs.

5. The second stage SOVA detector of claim 1 wherein the dynamic state reordering block computes a difference between the maximum likelihood path and all current survivors and provides the difference to a register exchange unit.

6. The second stage SOVA detector of claim 1 wherein the dynamic state reordering block processes S×

L data blocks and comprises S S-input multiplexors and 2*S XOR gates, and the complexity of the dynamic state reordering block is independent of L.

7. The second stage SOVA detector of claim 1 wherein the dynamic state reordering block processes S×

L data blocks and comprises a precoder, 2*S-input multiplexors and S*(log 2(S)+2) XOR gates, and the complexity of the dynamic state reordering block is independent of L.

8. The second stage SOVA detector of claim 1 wherein the dynamic state reordering block receives MLP and PMD from a first stage SOVA detector and the dynamic state reordering block comprises:

a MLST that processes the MLP and generates an AMLPS; and

a MPMDSEL that processes the PMD as a function of the AMLPS.

9. A method of second stage SOVA detecting, comprising:

receiving absolute state domain data and performing dynamic state reordering to provide relative state domain data and selection bit outputs;

receiving the relative state domain data outputs and the selection bit outputs at pipeline registers and providing pipelined outputs; and

receiving the pipelined outputs at a reliability update-register exchange unit and providing detected data bits and reliabilities.

10. The method of claim 9 further comprising:

forming a signed numerical value where the sign represents the detected data bits and the numerical value represents the reliability.

11. The method of claim 9 further comprising:

providing the detected data bits as read channel data from a data storage device.

12. The method of claim 9 further comprising:

maintaining values of a current state of a maximum likelihood path and the maximum likelihood competitive path in the relative state domain data and selection bit outputs.

13. The method of claim 9 further comprising:

computing a difference between the maximum likelihood path and all current survivors and provides the difference to a register exchange unit.

14. The method of claim 9 further comprising:

processing S×

L data blocks with S S-input multiplexors and 2*S XOR gates in a dynamic state reordering block in which the complexity of the dynamic state reordering block is independent of L.

15. The method of claim 9 further comprising:

processing S×

L data blocks with a precoder, 2*S-input multiplexors and S*(log 2(S)+2) XOR gates where the complexity of the dynamic state reordering block is independent of L.

16. The method of claim 9 further comprising:

receiving MLP and PMD from a first stage SOVA detector and the dynamic state reordering comprises;

processing the MLP with a MLST that generates an AMLPS; and

processing the PMD with a MPMDSEL as a function of the AMLPS.

17. A second stage SOVA detector, comprising:

dynamic state reordering means for receiving absolute state domain data and for providing relative state domain data and selection bit outputs;

pipeline registers receiving the relative state domain data outputs and the selection bit outputs and providing pipelined outputs; and

a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.

18. The second stage SOVA detector of claim 17 wherein the detected data bits and the reliabilities form a signed numerical value, and the sign represents the data and the numerical value represents the reliability.

19. The second stage SOVA detector of claim 17 wherein the detected data bits comprise read channel data from a data storage device.

20. The second stage SOVA detector of claim 17 wherein the dynamic state reordering means maintains values of current state of maximum likelihood path and the maximum likelihood competitive path in the relative state domain data and selection bit outputs.