Method of manufacturing a closed cell trench MOSFET
First Claim
1. A method of fabricating a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:
- epitaxial depositing a first semiconductor layer upon a substrate, wherein said first semiconductor layer is doped with a first type of impurity;
etching a plurality of trenches in said first semiconductor layer, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and a second set of said plurality of trenches are substantially normal-to-parallel with respect to said first set of said plurality of trenches;
forming a dielectric proximate said plurality of trenches;
implanting said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches and not proximate the bottoms of said second set of said plurality of trenches;
depositing a second semiconductor layer in said plurality of trenches;
implanting a first portion of said first semiconductor layer with a second type of impurity; and
implanting a second portion of said first semiconductor layer proximate said dielectric with said first type of impurity.
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Accused Products
Abstract
Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.
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Citations
20 Claims
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1. A method of fabricating a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:
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epitaxial depositing a first semiconductor layer upon a substrate, wherein said first semiconductor layer is doped with a first type of impurity; etching a plurality of trenches in said first semiconductor layer, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and a second set of said plurality of trenches are substantially normal-to-parallel with respect to said first set of said plurality of trenches; forming a dielectric proximate said plurality of trenches; implanting said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches and not proximate the bottoms of said second set of said plurality of trenches; depositing a second semiconductor layer in said plurality of trenches; implanting a first portion of said first semiconductor layer with a second type of impurity; and implanting a second portion of said first semiconductor layer proximate said dielectric with said first type of impurity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of fabricating a closed cell trench metal-oxide semiconductor field effect transistor (TMOSFET) comprising;
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depositing a first portion of a first semiconductor layer upon a substrate, wherein said first semiconductor layer is doped with a first type of impurity; doping said first portion of said first semiconductor layer, wherein a plurality of buried doped regions are formed in said first portion of said first semiconductor layer; depositing a second portion of said first semiconductor layer upon said first portion of said first semiconductor layer; etching a plurality of trenches in said first semiconductor layer, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and aligned to said plurality of buried doped reunions and wherein a second set of said plurality of trenches are substantially normal-to-parallel with respect to said first set of said plurality of trenches; forming a dielectric proximate said plurality of trenches; depositing a second semiconductor layer in said plurality of trenches; doping a body region of said first semiconductor layer between said plurality of trenches with a second type of impurity; and doping a source region of said first semiconductor layer between said plurality of trenches and said first region of said first semiconductor layer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification