Nonplanar transistors with metal gate electrodes

• US 7,361,958 B2
• Filed: 09/30/2004
• Issued: 04/22/2008
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Doczy, Mark
• Primary Examiner(s): Cao; Phat X
• Application Number:
  US10/956,279
• Publication Number:
  US 20060071275A1
• Time in Patent Office: 1,300 Days
• Field of Search: 257/391, 257/392, 257/369, 257/371
• US Class Current: 257/369
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: Y10S 438/926 Dummy metallization
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A CMOS integrated circuit comprising:

a PMOS device having a gate dielectric layer formed in an n channel region with a first dopant concentration and a pair of p-type source/drain regions and a gate electrode having a first material composition, said first material composition comprising a metal, said pair of p-type source/drain regions comprising a p-type source/drain extension region and a p-type source/drain contact region, said p-type source/drain extension regions having a second dopant concentration; and

an NMOS device having a gate dielectric layer formed on a p-type channel region with a third dopant concentration and a pair of n-type source/drain regions and a gate electrode comprising said first composition, said pair of n-type source/drain regions comprising an n-type source/drain extension region and an n-type source/drain contact region, said n-type source/drain extension regions having a fourth dopant concentration,

wherein said first dopant concentration and second dopant concentration and said third dopant concentration and said fourth dopant concentration are such that said gate electrode for said PMOS device exhibits a work function between 0.9-1.1 eV different than the work function exhibited by said gate electrode for said NMOS device.

2. The CMOS integrated circuit of claim 1 wherein said first dopant concentration is between intrinsic and 4×

10¹⁹ atoms/cm³, said second dopant concentration is between 1×

10¹⁹-1×

10²¹ atoms/cm³, said third dopant concentration is between intrinsic and 4×

10¹⁹ atoms/cm³, and said fourth dopant concentration is between 1×

10¹⁹-1×

10²¹ atom/cm³.

3. The CMOS integrated circuit of claim 1 wherein said PMOS gate electrode and said NMOS gate electrode comprise a midgap work function material.

4. The CMOS integrated circuit of claim 3 wherein said midgap work function material is selected from the group consisting of the carbides or nitrides of titanium or tantalum.

5. A CMOS integrated circuit comprising:

a p-type nonplanar semiconductor device comprising a gate electrode formed from a first film stack including a metal formed on a gate dielectric layer formed on and around an n-type semiconductor body defining the channel region, said channel region having a first range of doping concentration and a pair of p-type source/drain regions on opposite sides of said gate electrode, said pair of source/drain regions comprising a source/drain extension region and a source/drain contact region;

an n-type nonplanar semiconductor device comprising a gate electrode formed from said first film stack formed on a gate dielectric layer formed on and around a p-type semiconductor body defining a channel region having a p-type conductivity of the first range of concentration and a pair of n-type source/drain regions on opposite sides of said gate electrode, said pair of n-type source/drain regions comprising source/drain extension region and a source/drain contact region; and

wherein the doping of said n-type source/drain extension regions and said p-type channel region of said n-type nonplanar semiconductor device and said doping of said p-type source/drain extension regions and said n-type channel region of said p-type nonplanar device create an 0.9-1.1 eV difference in the work function of said gate electrode of said p type nonplanar semiconductor device and said gate electrode of said n-type nonplanar semiconductor device.

6. The CMOS integrated circuit of claim 5 wherein said n-type channel region has a doping concentration between intrinsic and 4×

10¹⁹ atoms/cm³ and said p-type source/drain regions extension regions have a doping concentration between 1×

10¹⁹-1×

10²¹ atoms/cm³ and said p-type channel region having a doping concentration between intrinsic and 4×

10¹⁹ atoms/cm³ and said n-type source/drain extension regions have doping concentration between 1×

10¹⁹-1×

10²¹ atom/cm³.

7. The CMOS integrated circuit of claim 5 wherein said gate electrode of said p-type nonplanar device and said gate electrode of said n-type nonplanar device are each formed from material having a midgap work function.

8. A CMOS integrated circuit comprising:

a PMOS device having a gate dielectric an n channel region with a first dopant concentration and a pair of p-type source/drain regions and a gate electrode having a first material composition including a metal and a stand alone work function of between 4.3-4.8 eV, said pair of p-type source/drain regions comprising a p-type source/drain extension region and a p-type source/drain contact region, said p-type source/drain extension regions having a second dopant concentration; and

an NMOS device having a gate dielectric formed on a p-type channel region with a third dopant concentration and a pair of n-type source/drain regions and a gate electrode comprising a second composition with a stand alone work function of between 4.3-4.8 eV, said pair of n-type source/drain regions comprising an n-type source/drain extension region and an n-type source/drain contact region, said n-type source/drain extension regions having a fourth dopant concentration; and

wherein said first dopant concentration and second dopant concentration and said third dopant concentration and said fourth dopant concentration are such that said gate electrode for said PMOS device exhibits a work function between 4.9-5.2 eV and said gate electrode for said NMOS device exhibits a work function between 3.9-4.2 eV.

9. The CMOS integrated circuit of claim 8 wherein said first dopant concentration is between intrinsic and 4×

10¹⁹ atoms/cm³, said second dopant concentration is between 1×

10¹⁹-1×

10²¹ atom/cm³, said third dopant concentration is between intrinsic and 4×

10¹⁹ atoms/cm³, and said fourth dopant concentration is between 1×

10¹⁹-1×

10²¹ atoms/cm³.

10. The CMOS integrated circuit of claim 8 wherein said first and second material composition comprise a material selected from the group consisting of the carbides or nitrides of titanium or tantalum.

11. A CMOS integrated circuit comprising:

a p-type nonplanar semiconductor device comprising a gate electrode formed from a first film stack with a stand alone work function of between 4.3-4.8 eV formed on a gate dielectric layer formed on and around an n-type semiconductor body defining the channel region, said channel region having a first range of doping concentration and a pair of p-type source/drain regions on opposite sides of said gate electrode, said pair of source/drain regions comprising a source/drain extension region and a source/drain contact region;

an n-type nonplanar semiconductor device comprising a gate electrode formed from a second film stack including a metal and a stand alone work function of between 4.3-4.8 eV formed on a gate dielectric layer formed on and around a p-type semiconductor body defining a channel region having a p-type conductivity of the first range of concentration and a pair of n-type source/drain regions on opposite sides of said gate electrode, said pair of n-type source/drain regions comprising source/drain extension region and a source/drain contact region; and

wherein the doping of said n-type source/drain extension regions and said p-type channel region of said n-type nonplanar semiconductor device and said doping of said p-type source/drain extension regions and said n-type channel region of said p-type nonplanar device are such said gate electrode for said p-type nonplanar device exhibits a work function between 4.9-5.2 eV and said gate electrode for said n-type nonplanar device exhibits a work function between 3.9-4.2 eV.

12. The CMOS integrated circuit of claim 11 wherein said n-type channel region has a doping concentration between intrinsic and 4×

10¹⁹ atoms/cm³ and said p-type source/drain regions extension regions have a doping concentration between 1×

10¹⁹-1×

10²¹ atoms/cm³ and said p-type channel region having a doping concentration between intrinsic and 4×

10¹⁹ atoms/cmand said n-type source/drain extension regions have doping concentration between 1×

10¹⁹-1×

10²¹ atoms/cm³.

13. The CMOS integrated circuit of claim 11 wherein said metal of said first film stack and said metal of said second film stack are selected from the group consisting of the carbides or nitrides of titanium or tantalum.