Stacked imager package
First Claim
1. A chip package, comprising:
- a first chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by through via conductors extending through said first chip from said backside metallurgy to said pads; and
a second chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said first chip by an array of interchip solder bumps.
4 Assignments
0 Petitions
Accused Products
Abstract
An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
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Citations
11 Claims
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1. A chip package, comprising:
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a first chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by through via conductors extending through said first chip from said backside metallurgy to said pads; and a second chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said first chip by an array of interchip solder bumps.
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2. A chip package, comprising:
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an imaging chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by conductors extending from said backside metallurgy to said pads; and a logic chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said imaging chip by an array of interchip solder bumps. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification