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Stacked imager package

  • US 7,361,989 B1
  • Filed: 09/26/2006
  • Issued: 04/22/2008
  • Est. Priority Date: 09/26/2006
  • Status: Active Grant
First Claim
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1. A chip package, comprising:

  • a first chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by through via conductors extending through said first chip from said backside metallurgy to said pads; and

    a second chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said first chip by an array of interchip solder bumps.

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