Network traffic management system with floating point sorter
First Claim
1. An integrated circuit comprising:
- M sorter blocks, wherein each sorter block has a user-selectable number of entries of one or more entries, each entry comprises a time stamp value, represented in a floating point format, and a connection value, there are a total of N entries for all the M sorter blocks, and M is an integer 2 or greater,wherein upon receiving a first packet of information on a first port, storing a first time stamp, represented in a floating point format, and a first connection value in a first entry of a first sorter,upon receiving a second packet of information on the first port, storing a second time stamp, represented in a floating point format, and a second connection value in a second entry of the first sorter,upon receiving a third packet of information on a second port, storing a third time stamp, represented in a floating point format, and a third connection value in a first entry of a second sorter, andupon receiving a fourth packet of information on the second port, storing a fourth time stamp, represented in a floating point format, and a fourth connection value in a second entry of the second sorter.
1 Assignment
0 Petitions
Accused Products
Abstract
A technique to implement a network traffic management system with an integrated multidimensional floating point sorter (306) is to store data such that it may be retrieved in a sorted fashion. Entries are stored (407) into a memory according to time stamp value, represented in a floating point format, and the time stamp value is divided (412) into at least two portions, exponent and mantissa. The memory is organized as a pointer memory (505, 508, 513, and 520). An integrated multidimensional floating point sorter may be implemented using integrated circuit technology using one or more integrated circuits (306). These integrated circuits may be used in management of network traffic, and provides quality of service (QoS) or class of service (CoS) control.
33 Citations
28 Claims
-
1. An integrated circuit comprising:
-
M sorter blocks, wherein each sorter block has a user-selectable number of entries of one or more entries, each entry comprises a time stamp value, represented in a floating point format, and a connection value, there are a total of N entries for all the M sorter blocks, and M is an integer 2 or greater, wherein upon receiving a first packet of information on a first port, storing a first time stamp, represented in a floating point format, and a first connection value in a first entry of a first sorter, upon receiving a second packet of information on the first port, storing a second time stamp, represented in a floating point format, and a second connection value in a second entry of the first sorter, upon receiving a third packet of information on a second port, storing a third time stamp, represented in a floating point format, and a third connection value in a first entry of a second sorter, and upon receiving a fourth packet of information on the second port, storing a fourth time stamp, represented in a floating point format, and a fourth connection value in a second entry of the second sorter. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. An integrated circuit comprising:
-
a first sorter block portion of the integrated circuit comprising N(1) entries, wherein each entry comprises a connection value and a time stamp value, represented by a mantissa and exponent, entries in the first sorter block are sorted according to their time stamp value, and the number of entries N(1) is user-selectable; and a second sorter block portion of the integrated circuit comprising N(2) entries, wherein each entry comprises a connection value and a time stamp value, represented by a mantissa and exponent, entries in the second sorter block are sorted according to their time stamp value, and the number of entries N(2) is user selectable, wherein upon receiving a first packet of information on a first port, storing a first time stamp, represented by a mantissa and exponent, and a first connection value in a first entry of the first sorter block, upon receiving a second packet of information on the first port, storing a second time stamp, represented by a mantissa and exponent, and a second connection value in a second entry of the first sorter block, upon receiving a third packet of information on a second port storing a third time stamp, represented by a mantissa and exponent, and a third connection value in a first entry of the second sorter block, and upon receiving a fourth packet of information on the second port, storing a fourth time stamp, represented by a mantissa and exponent, and a fourth connection value in a second entry of the second sorter block. - View Dependent Claims (8, 9)
-
-
10. An integrated circuit comprising:
-
first control circuitry to implement a first sorter block comprising N(1) entries, wherein each entry comprises a connection value and a time stamp value, represented by a fraction multiplied by a power of a number base indicated by an exponent, entries in the first sorter block are sorted according to their time stamp value, and the number of entries N(1) is user-selectable; and second control circuitry to implement a second sorter block comprising N(2) entries, wherein each entry comprises a connection value and a time stamp value, represented by a fraction multiplied by a power of a number base indicated by an exponent, entries in the second sorter block are sorted according to their time stamp value, and the number of entries N(2) is user-selectable, wherein upon receiving a first packet of information on a first port, storing a first time stamp, represented by a fraction multiplied by a power of a number base indicated by an exponent, and a first connection value in a first entry of the first sorter block, upon receiving a second packet of information on the first port, storing a second time stamp, represented by a fraction multiplied by a power of a number base indicated by an exponent, and a second connection value in a second entry of the first sorter block, upon receiving a third packet of information on a second port, storing a third time stamp, represented by a fraction multiplied by a power of a number base indicated by an exponent, and a third connection value in a first entry of the second sorter block, and upon receiving a fourth packet of information on the second port, storing a fourth time stamp, represented by a fraction multiplied by a power of a number base indicated by an exponent, and a fourth connection value in a second entry of the second sorter block. - View Dependent Claims (11, 12)
-
-
13. An integrated circuit comprising:
-
control circuitry to implement M sorter blocks, wherein each sorter block has a user-selectable number of entries of one or more entries, each entry comprises a time stamp value, represented in a floating point format, and a connection value, there are a total of N entries for all the M sorter blocks, and M is an integer 2 or greater, wherein upon receiving a first packet of information on a first port, storing a first time stamp, represented in a floating point format, and a first connection value in a first entry of a first sorter, upon receiving a second packet of information on the first port, storing a second time stamp, represented in a floating point format, and a second connection value in a second entry of the first sorter, upon receiving a third packet of information on a second port, storing a third time stamp, represented in a floating point format, and a third connection value in a first entry of a second sorter, and upon receiving a fourth packet of information on the second port storing a fourth time stamp, represented in a floating point format, and a fourth connection value in a second entry of the second sorter. - View Dependent Claims (14)
-
-
15. A method comprising:
-
receiving a first entry to be stored in a memory location, wherein the first entry has a time stamp value, represented in a floating point format, and a data value; dividing the time stamp value of the first entry into two or more portions, a first time stamp portion and a second time stamp portion; providing a first pointer memory structure, referred to by a first pointer address, having a head and a body, wherein the head comprises a bit map field and a pointer-to-body field; providing a second pointer memory structure having a head and a body, wherein the head comprises a bit map field and a pointer-to-body field; storing a second pointer address in the body of the first pointer memory structure based on the first time stamp portion; and indicating the position in the head of the first pointer, wherein the second pointer address points to the second pointer memory structure. - View Dependent Claims (16, 17)
-
-
18. A method comprising:
-
receiving an entry comprising a binary time stamp; converting the binary time stamp into a time stamp, represented by a mantissa and an exponent, having a first time stamp portion and a second time stamp portion; providing a first pointer memory structure, referenced using a first pointer address and having a head and a body, wherein the head comprises a bit map field comprising two or more bits and the body comprises two or more memory positions, each bit in the bit map field representing one of the two or more memory positions; initializing the two or more bits of the head of the first pointer memory structure to a first state; when storing a second pointer address in a first memory position of the two or more memory positions, changing a first bit of the two or more bits of the head of the first pointer memory structure to a second state; and when storing the second pointer address in a second memory position of the two or more memory positions, changing a second bit of the two or more bits of the head of the first pointer memory structure to the second state. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
-
Specification