Network processing pipeline chipset for routing and host packet processing
First Claim
Patent Images
1. A network processing system, said system comprising:
- a host central processing unit (CPU) configured to virtualize host resources to provide multiple virtual host computers through a host media access controller (HM);
a network processing unit attached to each one of the virtual host computers and having a plurality of processing subunits for performing both router packet processing and host packet processing, wherein one of said plurality of processing subunits is the HM that is configured to communicate with a first virtual host computer of the multiple virtual host computers using standard networking protocols to;
indicate that a packet processing event has occurred and said network processing unit is unable to process a packet corresponding to said packet processing event, andforward said packet to host CPU for resolution;
a first software driver configured to manage communications between said host CPU and said network processing unit for host packet processing; and
a second software driver configured to manage communications between said network processing unit and other processing units in said network processing system for router packet processing using standard networking protocols without involvement by the CPU.
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Abstract
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer'"'"'s chipset such that the host computer'"'"'s resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
95 Citations
37 Claims
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1. A network processing system, said system comprising:
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a host central processing unit (CPU) configured to virtualize host resources to provide multiple virtual host computers through a host media access controller (HM); a network processing unit attached to each one of the virtual host computers and having a plurality of processing subunits for performing both router packet processing and host packet processing, wherein one of said plurality of processing subunits is the HM that is configured to communicate with a first virtual host computer of the multiple virtual host computers using standard networking protocols to; indicate that a packet processing event has occurred and said network processing unit is unable to process a packet corresponding to said packet processing event, and forward said packet to host CPU for resolution; a first software driver configured to manage communications between said host CPU and said network processing unit for host packet processing; and a second software driver configured to manage communications between said network processing unit and other processing units in said network processing system for router packet processing using standard networking protocols without involvement by the CPU. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A network processing system, said system comprising:
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a host central processing unit (CPU); a system memory of said host CPU; a network processing unit having a plurality of processing subunits for performing both router packet processing and host packet processing, wherein one of said plurality of processing subunits is a media access controller interface (MI) subunit for communicating with at least one media access controller (MAC) to serve as an input and output point for traversal of packets, and to provide an asynchronous boundary interface between a first clock domain of said MAC and a second clock domain of said MI subunit; and a host media access controller (HM) for communicating directly with said MI subunit and said host CPU, wherein said HM accesses a plurality of push buffers that are stored in said system memory to transfer commands or data between said HM and said host CPU; and a first software driver configured to manage communications between said host CPU and said network processing unit for host packet processing, wherein the first software driver is configured to load host originated frames into the plurality of push buffers in order for the HM to select one push buffer from said plurality of push buffers by detecting how many of said plurality of push buffers that are allocated to store commands or data are not empty to produce non-empty push buffers for consumption by said MI and determine a priority of each non-empty push buffer. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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Specification