Auto-configured equalizer

• US 7,362,800 B1
• Filed: 07/12/2002
• Issued: 04/22/2008
• Est. Priority Date: 07/12/2002
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Stojanovic, Vladimir M., Zerbe, Jared L., Chen, Fred F.
• Primary Examiner(s): ODOM, CURTIS B
• Application Number:
  US10/195,130
• Time in Patent Office: 2,111 Days
• Field of Search: 375/226, 375229-236
• US Class Current: 375/226
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end

Abstract

An signal communication device having an auto-configured equalizer. The signal communication device includes a scoping circuit, buffer circuit, select circuit and equalizing circuit. A test signal is transmitted to the signal communication device via a signal path. The scoping circuit generates a waveform trace of the test signal, the waveform trace indicating time interval between receipt of a transition in the test signal and receipt of a reflection of the transition. The buffer circuit stores a plurality of data values that correspond to data signals received via the signal path. The select circuit selects one of the plurality of data values from the buffer circuit based on the time interval indicated by the waveform trace. The equalizing circuit generates an equalizing signal based on the selected data value.

Claims

1. An apparatus comprising:

a scoping circuit to generate a waveform trace of a test signal received via a signal path, the waveform trace indicating a time interval between receipt of a transition of the test signal and receipt of a reflection of the transition;

a buffer circuit to store a plurality of data values that correspond to data signals received via the signal path;

a select circuit coupled to the buffer circuit to select therefrom, according to the time interval indicated by the waveform trace, a first data value of the plurality of data values; and

an equalizing circuit to generate an equalizing signal based, at least in part, on the first data value.

2. The apparatus of claim 1 wherein the scoping circuit comprises:

a signal generator to generate a local version of the test signal; and

a comparator to compare the local version of the test signal with the test signal received via the signal path.

3. The apparatus of claim 2 wherein the scoping circuit further comprises a logic circuit to adjust a phase offset of a clock signal used to time reception of the test signal received via the signal path.

4. The apparatus of claim 3 wherein the test signal received via the signal path is a repeating test signal, and wherein the logic circuit is adapted to incrementally adjust the phase offset of the clock signal after each N repetitions of the test signal, N being an integer greater than zero.

5. The apparatus of claim 4 wherein the each of the incrementally adjusted phase offsets of the clock signal correspond to a sample point in the waveform trace.

6. The apparatus of claim 2 wherein the scoping circuit further comprises a logic circuit to adjust a threshold voltage, the threshold voltage being used to determine a data value represented by the test signal received via the signal path.

7. The apparatus of claim 6 wherein the test signal received via the signal path is a repeating test signal, and wherein the logic circuit is adapted to incrementally adjust the threshold voltage after each N repetitions of the test signal, N being an integer greater than zero.

8. The apparatus of claim 7 wherein logic circuit is adapted to record the threshold voltage at which the comparator indicates a mismatch between the test signal received via the signal path and the local version of the test signal, the threshold voltage at which the comparator indicates the mismatch being indicative of the test signal voltage level at an instant in time.

9. The apparatus of claim 8 wherein the waveform trace is formed by a sequence of test signal voltage level determinations, each test signal voltage level determination corresponding to a threshold voltage at which the comparator indicates a mismatch between the test signal received via the signal path and the local version of the test signal.

10. The apparatus of claim 1 wherein the scoping circuit comprises circuitry to generate a select value based on the time interval between receipt of the transition of the test signal and receipt of the reflection of the transition.

11. The apparatus of claim 10 wherein the select circuit is coupled receive the select value from the scoping circuit, the select circuit being adapted to select the first data value according to the select value.

12. The apparatus of claim 1 further comprising a configuration circuit coupled to the scoping circuit and to the select circuit, the scoping circuit being adapted to generate a select value based on the time interval and to store the select value in the configuration circuit, the select circuit being adapted to select the first data value based on the select value.

13. A method of operation within an integrated circuit device, the method comprising:

generating a waveform trace of a test signal received via a signal path;

selecting, based on the waveform trace, a first data value of a plurality of data values that correspond to signals received via the signal path; and

generating an equalizing signal based on the first data value,

wherein generating the waveform trace of the test signal comprises;

generating a local version of the test signal; and

comparing the local version of the test signal with the test signal received via the signal path,

wherein generating the waveform trace of the test signal comprises;

incrementally adjusting a phase of a clock signal used to time reception of the test signal to capture samples of the test signal at different timing offsets within a window of the test signal.

14. The method of claim 13 wherein the test signal is a repeating test signal, and wherein incrementally adjusting the phase of the clock signal comprises incrementally adjusting the phase of the clock signal after each N repetitions of the test signal, N being an integer greater than zero.

15. The method of claim 14 wherein each incrementally adjusted phase of the clock signal corresponds to a sample point in the waveform trace.

16. The method of claim 13 wherein generating the waveform trace of the test signal further comprises incrementally adjusting a threshold voltage used to determine a data value represented by the test signal.

17. The method of claim 16 wherein the test signal is a repeating test signal, and wherein incrementally adjusting the threshold voltage comprises incrementally adjusting the threshold voltage after each N repetitions of the test signal, N being an integer greater than zero.

18. The method of claim 17 further comprising recording the threshold voltage at which a comparison of the local version of the test signal with the test signal received via the signal path yields a mismatch, the threshold voltage at which the comparison yields a mismatch being indicative of a voltage level of the test signal at an instant in time.

19. A signaling system comprising:

a transmit device including a transmitter, data selector and pattern generator, the data selector being adapted to select the pattern generator to provide a sequence of values to be transmitted by the transmitter during a scoping mode of operation of the transmit device;

a signal path coupled to the transmitter of the transmit device; and

a receive device including a receiver, receive-side pattern generator, comparator, select circuit, buffer, and equalizer, the receiver being coupled to the signal path to receive the sequence of values transmitted by the transmitter, the comparator being coupled to the receiver and the receive-side pattern generator and adapted to compare the sequence of values received by the receiver with a locally generated sequence of values generated by the receive-side pattern generator, the select circuit being adapted to select one of a plurality of storage elements within the buffer based on the comparison of the received sequence of values and the locally generated sequence of values, the equalizer being coupled to receive a data value from the one of the plurality of storage elements selected by the select circuit and being adapted to generate an equalizing signal based, at least in part, on the data value.

20. The system of claim 19 wherein the receive device further comprises a logic circuit to incrementally adjust a phase of a clock signal used to time reception of the sequence of values to achieve a plurality of incrementally phase-offset samples of each value of the sequence of values.

21. The system of claim 19 wherein the receive device further comprises a logic circuit to incrementally adjust a threshold voltage used to resolve each value of the received sequence of values to one of a plurality of possible digital values.

22. A method of operation within a signaling system, the method comprising:

receiving a test signal via a signal path;

comparing the test signal to a separately generated version of the test signal to determine a time interval between reception of a transition in the test signal and reception of a reflection of the transition;

selecting one of a plurality of storage elements according to the time interval; and

generating an equalizing signal based on contents of the one of the plurality of storage elements.

23. The method of claim 22 further comprising transmitting the test signal on the signal path during a scoping mode of operation within a transmit device of the signaling system.

24. The method of claim 23 wherein transmitting the test signal on the signal path comprises selecting, within the transmit device, a pattern generator to provide a sequence of values to be transmitted as the test signal.

25. The method of claim 24 wherein the sequence of values represents a pulse.

26. The method of claim 24 wherein comparing the test signal to the separately generated version of the test signal to determine the time interval between reception of the transition in the test signal and reception of the reflection of the transition comprises determining a time interval between reception of the pulse and reception of a reflection of the pulse.

27. The method of claim 22 wherein comparing the test signal to the separately generated version of the test signal to determine the time interval between reception of the transition in the test signal and reception of the reflection of the transition comprises:

incrementally adjusting a phase offset of a clock signal used to capture samples of the test signal; and

incrementally adjusting a threshold voltage used to resolve each of the samples of the test signal to a digital value.

28. The method of claim 27 wherein comparing the test signal to the separately generated version of the test signal to determine the time interval between reception of the transition in the test signal and reception of the reflection of the transition further comprises generating a waveform trace of the test signal based on incrementally adjusted threshold voltages at which samples of the test signal are resolved to digital values that do not match digital values within the separately generated version of the test signal.

29. The method of claim 27 wherein comparing the test signal to the separately generated version of the test signal to determine the time interval between reception of the transition in the test signal and reception of the reflection of the transition further comprises determining a time interval between a pulse within the waveform trace and a reflection of the pulse.