Apparatus and method for generating scrambling code in UMTS mobile communication system

• US 7,362,867 B1
• Filed: 07/07/2000
• Issued: 04/22/2008
• Est. Priority Date: 07/07/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Hee-Won, Kim, Jae-Yoel
• Primary Examiner(s): Zand; Kambiz
• Assistant Examiner(s): COLIN, CARL G
• Application Number:
  US09/611,518
• Time in Patent Office: 2,846 Days
• Field of Search: 370/335, 370/342, 380/239, 380/209, 380/255, 380 11- 15, 380219-221, 380/268, 380/275, 380/33, 380/34, 380/47, 380/140, 380/273, 375/155, 375/200, 375/150, 375/152
• US Class Current: 380/275
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H04J 13/0025 M-sequences
• CPC Class Codes: H04J 13/0029 Gold
• CPC Class Codes: H04J 13/10 Code generation
• CPC Class Codes: H04J 13/102 Combining codes
• CPC Class Codes: H04J 13/107 by concatenation

Abstract

A scrambling code generating apparatus of a downlink transmitter in a UMTS mobile communication system, which uses one primary scrambling code for separation of base stations and multiple secondary scrambling codes for channel separation. The apparatus includes a first m-sequence generator for generating a first m-sequence and a second m-sequence generator for generating a second m-sequence. A first summer adds the first and second m-sequences to generate the primary scrambling code. A plurality of first masking sections each shift the first m-sequence, and a plurality of second masking sections corresponding to the respective first masking sections each shifts the second m-sequence. A plurality of second summers each adds one of the first shifted m-sequences with the second m-sequence corresponding to the first m-sequence. The output of the second summers thus generates the multiple secondary scrambling codes.

Claims

1. A method for generating a primary scrambling code, the method comprising the steps of:

generating a first m-sequence from a first m-sequence generator including first shift registers having first shift register values a_i, wherein i=0 to c−

1 and where c is the total number of the registers;

generating a second m-sequence from a second m-sequence generator including second shift registers having values b_j, wherein j=0 to c−

1, and where c is the total number of the registers;

masking the first shift register values a_i with a first set or mask values K_i, wherein i=0 to c−

1 to generate a third m-sequence;

adding the first m-sequence with the second m-sequence to generate a primary scrambling code; and

adding the third m-sequence and the second m-sequence to generate a secondary scrambling code;

wherein, the masking step shifts the first m-sequence cyclically by L chips to generate an L^th secondary scrambling code associated with the primary scrambling code.

2. The method of claim 1, wherein the primary scrambling code is one of a plurality primary scrambling codes and a K^th primary scrambling code is a ((K−

1)*M+K)^th gold code, where M is a total number of secondary scrambling codes per primary scrambling code and 1<

K<

512.

3. The method of claim 1, wherein the secondary scrambling codes associated with a K^th primary scrambling code are from ((K−

1)*M+K+1)^th to (K*M+K)^th gold codes, where M is a total number of secondary scrambling codes per primary scrambling code and 1<

K<

512.

4. The method of claim 1, wherein 1<

L<

M, where M is a total number of secondary scrambling codes per primary scrambling code.

5. The method of claim 1, wherein the masking step is expressed by Σ

(k_i×

a_i).

6. The method of claim 1, further comprising:

masking the first shift register values a_i with a second set of mask values K_j to generate a fourth m-sequence, wherein j=0 to c−

1; and

adding the fourth m-sequence and the second m-sequence to generate an N^th secondary scrambling code associated with the primary scrambling code;

wherein, the masking step shifts the first m-sequence cyclically by N chips to generate an N^th secondary scrambling code.

7. The method of claim 6, wherein 1<

N<

M, where M is a total number of secondary scrambling codes per primary scrambling code.

8. The method of claim 1, further comprising the step of delaying at least one of the primary scrambling code and secondary scrambling code to produce a Q-channel component, wherein the primary scrambling code and secondary scrambling code are I-channel components.

9. A scrambling code generator, comprising:

a first m-sequence generator to generate a first m-sequence by using a plurality of first registers with first shift register values a_i, wherein i=0 to c−

1 and where c is the total number of the first registers;

a second m-sequence generator to generate a second m-sequence by using a plurality of second registers with second shift register values b_j, wherein j=0 to c−

1 and where c is the total number of second registers;

a masking section to mask the first shift register values a_i with a first set of mask values K_i to generate a third m-sequence, wherein i=0 to c−

1 to generate a third m-sequence;

a first adder to add the first m-sequence and the second m-sequence to generate a primary scrambling code; and

a second adder to add the third m-sequence and the second m-sequence to generate a secondary scrambling code,

wherein the masking section shifts the first m-sequence cyclically by L chips to generate an L^th secondary scrambling code associated with the primary scrambling code.

10. The scrambling code generator of claim 9, wherein the primary scrambling code is one of a plurality of primary scrambling codes and a K^th primary scrambling code is a ((K−

1)*M+K)^th gold code, where M is a total number of secondary scrambling codes per primary scrambling code and 1<

K<

512.

11. The scrambling code generator of claim 10, wherein the secondary scrambling codes associated with the K^th primary scrambling code are ((K−

1)*M+K+1)^th to (K*M+K)^th gold codes.

12. The scrambling code generator of claim 9, further comprising:

a second masking section to mask the first shift register values a_i, with a second set of mask values K_j, wherein j=0 to c−

1, to generate a fourth m-sequence; and

a third adder to add the fourth m-sequence and the second m-sequence to generate an N-th secondary scrambling code associated with the primary scrambling code,

wherein the second masking section shifts the first m-sequence cyclically by N chips to generate the N^th secondary scrambling code.

13. The scrambling code generator of claim 9, wherein the masking section shifts the first m-sequence cyclically by masking the first shift register values a_i in accordance with Σ

(K_i×

a_i).

14. The scrambling code generator of claim 9, wherein the first m-sequence generator cyclically shifts the first shift register values and the second m-sequence generator cyclically shifts the second shift register values.

15. The scrambling code generator of claim 9, wherein the first m-sequence generator adds predetermined shift register values of the first shift registers based on a first generating polynomial of the first m-sequence, right shifts the first shift register values a_i of the first shift registers, and replaces the first register value a_c−

1 with the result of the addition of the predetermined register values.

16. The scrambling code generator of claim 9, wherein the first m-sequence generator adds a first shift register value a₀ with a first shift register a₇ to form a next first shift register a_c−

1.

17. The scrambling code generator of claim 9, wherein the second m-sequence generator adds predetermined shift register values of the second shift registers based on a second generating polynomial of the second m-sequence, right shifts the second shift register values b_j of the second shift registers, and replaces the second register value b_c−

1 with the result of the addition of the predetermined register values.

18. The scrambling code generator of claim 9, wherein the second m-sequence generator adds a second shift register value b₀ with a second shift register value b₅, b₇, and a second shift register value b₁₀ to form a next second shift register value b_c−

1.

19. The apparatus of claim 9, further comprising a means for delaying at least one of the primary scrambling code and the secondary scrambling code to produce Q-channel component, wherein the primary scrambling code and the secondary scrambling code are I-channel components.

20. A method for generating scrambling codes in mobile communication system having a scrambling code generator, the method comprising the steps of:

generating a ((K−

1)*M+K)^th gold code as a K^th primary scrambling code, where K is a natural number and M is a total number of secondary scrambling codes per one primary scrambling code; and

generating ((K−

1)*M+K+1)^th through (K*M+K)^th gold codes as secondary scrambling codes associated with the K^th primary scrambling code,

wherein an L^th Gold code is generated by adding an (L−

1)-times shifted first m-sequence and a second m-sequence.

21. The method as claimed in claim 20, wherein K is a primary scrambling code number and 1≦

K≦

512.

22. The method as claimed in claim 21, wherein the first m-sequence is generated from a first shift register memory having a plurality of first shift registers with first shift register values a_i, wherein i=0 to c−

1 and where c is the total number of the first registers and the (L−

1)-times shifted first m-sequence is generated by masking the first shift register values a_i with mask values K_i, where i=0 to c−

1.

23. The method as claimed in claim 22, wherein the masking is performed according to:

Σ

(K_i×

a_i).

24. The method as claimed in claim 20, wherein the generated primary scrambling code and secondary scrambling code are I-channel components and the method further comprises delaying at least one of the primary scrambling code and secondary scrambling code to produce Q-channel components.

25. An apparatus for generating scrambling codes in mobile communication system having a scrambling code generator, comprising:

a first m-sequence generator to generate a first m-sequence;

a second m-sequence generator to generate a second m-sequence; and

at least one adder for generating a ((K−

1)*M+K)^th Gold code as a K^th primary scrambling code by adding a (((K−

1)*M+K)−

1)-times shifted first m-sequence and the second m-sequence,

wherein K is a natural number and M is a total number of secondary scrambling codes per one primary scrambling code.

26. The apparatus of claim 25, wherein the secondary scrambling codes of the K^th primary scrambling codes are the ((K−

1)*M+K+1)^th through (K*M+K)^th Gold codes.

27. The apparatus as claimed in claim 26, wherein K is a primary scrambling code number and 1≦

K≦

512.

28. The apparatus as claimed in claim 25, wherein the first m-sequence generator comprises a plurality of first registers with first shift register values a_i, wherein i=0 to c−

1 and where c is the total number of the first shift registers, and the scrambling code generator further comprising at least one masking section for generating the n-times shifted first m-sequence by masking the first shift register values a_i with mask values K_i, where i=0 to c−

1.

29. The apparatus as claimed in claim 28, wherein the masking is performed according to:

Σ

(K_i×

a_i).

30. The apparatus as claimed in claim 25, wherein the primary scrambling code and secondary scrambling code are I-channel components and the apparatus further comprises a means for delaying at least one of the primary scrambling codes and secondary scrambling code to produce Q-channel components.

31. A method for generating scrambling codes in mobile communication system having a scrambling code generator, comprising the steps of:

generating a first m-sequence;

generating a second m-sequence; and

generating a ((K−

1)*M+K)^th Gold code as a K^th primary scrambling code by adding a (((K−

1)*M+K)−

1)-times shifted first m-sequence and the second m-sequence,

wherein K is a natural number and M is a total number of secondary scrambling codes per one primary scrambling code.

32. The method as claimed in claim 31, further comprising generating ((K−

1)*M+K+1)^th to (K*M+K)^th Gold codes as secondary scrambling codes corresponding to the K^th primary scrambling code.

33. The method as claimed in claim 31, wherein K is a primary scrambling code number and 1≦

K≦

512.

34. The method as claimed in claim 31, wherein the first m-sequence is generated from a first shift register memory having a plurality of first shift registers with first shift register values a_i, wherein i=0 to c−

1 and where c is the total number of the first registers and the n-times shifted first m-sequence is generated by masking the first shift register values a_i with mask values K_i, where i=0 to c−

1.

35. The method as claimed in claim 34, wherein the masking is performed according to:

Σ

(K_i×

a_i).

36. The method as claimed in claim 31, wherein each scrambling code is used as an I-channel component and a Q-channel component, corresponding to the I-channel component, is generated by delaying the I-channel component for a predetermined time.