Interruption control system and method
First Claim
1. An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said interrupt control system comprising:
- an interruption message generator for decoding and identifying a message signaled interrupt (MSI) issued by said first peripheral device or said second peripheral device when interruption is to be conducted, and generating an interruption status indicating message in response to said message signaled interrupt (MSI);
a stop clock control module coupled to said interruption message generator and said CPU and de-asserting a stop clock signal that is previously asserted to have said CPU enter a power-saving state to have said CPU deactivate said power-saving state in response to said interruption status indicating message; and
an interruption status indicating path for transmitting said interruption status indicating message.
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Accused Products
Abstract
An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.
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Citations
15 Claims
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1. An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said interrupt control system comprising:
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an interruption message generator for decoding and identifying a message signaled interrupt (MSI) issued by said first peripheral device or said second peripheral device when interruption is to be conducted, and generating an interruption status indicating message in response to said message signaled interrupt (MSI); a stop clock control module coupled to said interruption message generator and said CPU and de-asserting a stop clock signal that is previously asserted to have said CPU enter a power-saving state to have said CPU deactivate said power-saving state in response to said interruption status indicating message; and an interruption status indicating path for transmitting said interruption status indicating message. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An interruption control system, comprising:
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a CPU; a south bridge chip comprising a stop clock control module asserting a stop clock signal to said CPU in a power-saving mode and de-asserting said stop clock signal in an interruption mode; a north bridge chip coupled to a bus bridge chip, decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device coupled to said south bridge chip or a second peripheral device coupled to said bus bridge chip, and generating an interruption status indicating message in response to said message signaled interrupt (MSI); and an interruption status indicating path for transmitting said interruption status indicating message from said north bridge chip to said stop clock control module of said south bridge chip to deactivate a power-saving state of said computer system in response to said interruption status indicating message. - View Dependent Claims (8, 9, 10, 11)
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12. An interruption control method of a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said method comprising steps of:
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issuing a message signaled interrupt (MSI) from said second peripheral device and transmitting said message signaled interrupt (MSI) to said north bridge chip via said bus bridge chip when an interruption is asserted by said second peripheral device; decoding and identifying said message signaled interrupt (MSI) issued by said second peripheral device, and generating an interruption status indicating message in response to said message signaled interrupt (MSI); and de-asserting a stop clock signal that is previously asserted by said south bridge chip to deactivate a power-saving state of said computer system in response to said interruption status indicating message transmitted to said south bridge chip. - View Dependent Claims (13, 14, 15)
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Specification