Method and system for terminating write commands in a hub-based memory system
First Claim
1. A method of processing write commands in a memory system having a memory hub architecture including a plurality of memory hubs coupled in a point-to-point architecture beginning with a first hub and ending with a last hub, the method comprising:
- applying a read command to the first hub in the system;
subsequent to applying the read command, applying a write command to the first hub in the system directed to a hub upstream from the hub to which the read command is directed, a time interval is defined between when the read and write commands are applied, the time interval is a function of the position of the downstream hub to which the read command is directed relative to the upstream hub to which the write command is directed;
determining in the first hub whether the write command is directed to that hub;
when the determination indicates the write command is directed to the first hub, terminating downstream forwarding of the write data;
when the determination indicates the write command is not directed to the first hub, forwarding the write data downstream to a second hub; and
repeating the operations of determining through when the determination indicates the write command is not directed for all required memory hubs.
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Accused Products
Abstract
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command'"'"'s write data on a downstream output port adapted to be coupled to a downstream memory hub.
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Citations
25 Claims
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1. A method of processing write commands in a memory system having a memory hub architecture including a plurality of memory hubs coupled in a point-to-point architecture beginning with a first hub and ending with a last hub, the method comprising:
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applying a read command to the first hub in the system; subsequent to applying the read command, applying a write command to the first hub in the system directed to a hub upstream from the hub to which the read command is directed, a time interval is defined between when the read and write commands are applied, the time interval is a function of the position of the downstream hub to which the read command is directed relative to the upstream hub to which the write command is directed; determining in the first hub whether the write command is directed to that hub;
when the determination indicates the write command is directed to the first hub, terminating downstream forwarding of the write data;when the determination indicates the write command is not directed to the first hub, forwarding the write data downstream to a second hub; and repeating the operations of determining through when the determination indicates the write command is not directed for all required memory hubs. - View Dependent Claims (2, 3, 4)
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5. A method of operating a system memory having a memory hub architecture, the system memory including a plurality of memory modules coupled in series beginning with a first memory module and ending with a last memory module, each memory module including a memory hub, and the method comprising:
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applying a read command to the first memory module; detecting in each memory hub whether a write command applied subsequent to the read command is directed to the corresponding memory module, a time interval is defined between when the read and Write commands are applied, the time interval is a function of the position of the memory module to which the read command is directed relative to the memory module to which the write command is directed; when the operation of detecting indicates the write command is directed to the corresponding module, terminating the forwarding of the write data to downstream memory modules. - View Dependent Claims (6, 7)
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8. A memory system, comprising:
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a system controller; and a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising; a plurality of memory devices; and a memory hub coupled to the memory devices and including a downstream input port adapted to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, and the memory hub operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, and the hub operable in a second mode when the write command is not directed to the module to provide the command on a downstream output port, the system controller configured to determine a timing between when the system controller applies a read command to a first memory module relative to when the system controller applies a write command to a second module that is upstream of the first module as a function of the position of the downstream module to which the read command is directed relative to the upstream module to which the write command is directed each memory hub except a last memory hub adapted to receive upstream memory responses from an adjacent downstream module and provide such responses to an adjacent upstream memory module. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A computer system, comprising:
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a processor; a system controller coupled to the processor; an input device coupled to the processor through the system controller; an output device coupled to the processor through the system controller; a storage device coupled to the processor through the system controller; and
a plurality of memory modules coupled to the system controller, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;a plurality of memory devices; and a memory hub coupled to the memory devices and including a downstream input port adapted to receive downstream memory requests, and the hub operable to process each received downstream memory request to determine whether the memory request includes a write command directed to the memory module, and the memory hub operable in a first mode when the write command is directed to the module to apply memory access signals to the memory devices, and the hub operable in a second mode when the write command is not directed to the module to provide the command on a downstream output port, the system controller configured to determine a timing between when the system controller applies a read command to a first memory module relative to when the system controller applies a write command to a second module that is upstream of the first module as a function of the position of the downstream module to which the read command is directed relative to the upstream module to which the write command is directed each memory hub except a last memory hub adapted to receive upstream memory responses from an adjacent downstream module and provide such responses to an adjacent upstream memory module. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification