Delivery of an interruption to an operating system

• US 7,363,536 B1
• Filed: 07/30/2004
• Issued: 04/22/2008
• Est. Priority Date: 07/30/2004
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Magenheimer, Daniel J., Gardner, Robert D.
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US10/903,218
• Time in Patent Office: 1,362 Days
• Field of Search: 714/3, 714/15, 712/228, 712/244
• US Class Current: 714/15
• CPC Class Codes: G06F 11/0712 in a virtual computing platform, e.g. logically partitioned systems
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

One embodiment of the invention is a method for handling an interruption during execution of an application on a computer system that uses a register stack, the method comprising receiving the interruption by a hypervisor, sending the interruption to an operating system for handling; if the register stack has a fault, then generating, by the operating system, another interruption that is delivered to the hypervisor; after receiving the another interruption, covering, by the hypervisor, the register stack; after covering the register stack, sending the interruption to the operating system for handling; and after handling, returning to execution of the application.

Claims

1. A method for handling an interruption during execution of an application on a computer system that uses a register stack, the method comprising:

receiving the interruption by a hypervisor;

sending the interruption to an operating system for handling;

if the register stack has a fault, then another interruption is delivered to the hypervisor;

after receiving the another interruption, covering, by the hypervisor, the register stack;

after covering the register stack, sending the interruption to the operating system for handling; and

after handling, returning to execution of the application.

2. The method of claim 1, wherein the interruption is an external interrupt.

3. The method of claim 1, wherein the interruption is caused by execution of the application.

4. The method of claim 1, further comprising:

after receiving the another interruption, and before covering, determining, by the hypervisor, whether the register stack has a fault.

5. The method of claim 4, wherein determining whether the register stack has a fault comprises:

examining a bit in a control register that maintains interruption status of the register stack.

6. The method of claim 1, wherein covering the register stack comprises:

changing a bit in a control register to place the register stack in a quiescent state.

7. The method of claim 1, further comprising:

after covering the register stack, after handling, and before returning to execution, uncovering the register stack by the hypervisor.

8. The method of claim 7, wherein uncovering the register stack comprises:

changing a bit in a control register to remove the register stack from a quiescent state.

9. The method of claim 1, wherein the hypervisor has a higher privilege level than the operating system.

10. The method of claim 1, wherein the operating system is one of a plurality of operating systems.

11. The method of claim 1, wherein the interruption is associated with the fault in the register stack.

12. The method of claim 1, wherein the interruption is one of two interruptions, one lower level interruption, and one higher level interruption, and the method further comprises:

ignoring the lower level interruption until the higher level interruption has been handled.

13. The method of claim 12, further comprising:

after handling the higher level interruption, repeating the sending the interruption to an operating system for handling for the lower level interruption.

14. A computer system comprising:

a hypervisor having a first privilege level;

at least one operating system (OS) that has a second privilege level that is lower than the first privilege level, wherein the OS is connected to the hypervisor such an interruption that is received by the hypervisor can be forwarded to the OS for handling;

at least one application that has a third privilege level that is lower than the second privilege level; and

a register stack that is used by at least one of the hypervisor, the OS, and the application during operations of the system;

wherein, if the register stack has a fault, then the hypervisor covers the register stack during handling of the interruption.

15. The system of claim 14 further comprising:

a control register that maintains an interruption status of the register stack.

16. The system of claim 14 further comprising:

a control register that controls that state of the register stack.

17. The system of claim 16 wherein changing a bit in the control register will place the register stack in a quiescent state.

18. The system of claim 14 wherein the at least one OS comprises a plurality of OSs and the at least one application comprises a plurality of applications.

19. A computer system that handles an interruption during execution of an application comprising:

means for sending the interruption to an operating system for handling;

means for covering a register stack if the register stack has a fault; and

means for handling the interruption that is operative while the register stack is covered; and

means for uncovering the register stack after operation of the means for handling;

wherein after the register stack is uncovered, the computer system returns to execution of the application.

20. The system of claim 19, further comprising:

means for determining whether the register stack has a fault;

wherein the means for determining uses a control register that maintains interruption status of the register stack.

21. The system of claim 19 wherein the means for covering changes a bit in a control register to place the register stack in a quiescent state.

22. The system of claim 19 wherein the means for uncovering changes a bit in a control register to remove the register stack from a quiescent state.

23. A tangible computer readable medium having instructions for causing a computer to execute a method comprising:

sending an interruption that occurred during execution of an application to an operating system (OS) for handling by the OS;

determining whether a register stack has a fault;

covering a register stack if the register stack has a fault; and

uncovering the register stack after handling of the interruption by the OS.

24. The tangible computer readable medium of claim 23 wherein the register stack is used by at least one of a hypervisor, the OS, and the application.

25. The tangible computer readable medium of claim 23 further comprising accessesing a control register that maintains an interruption status of the register stack.

26. The tangible computer readable medium of claim 23 further comprising accessesing a control register that controls that state of the register stack, and changes a bit in the control register to place the register stack in a quiescent state.