Error-detection cell for an integrated processor
First Claim
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1. An integrated cell for detecting a disturbance capable of affecting operation of a processor, comprising:
- non-volatile storage means, in the integrated cell, for storing at least one value of verification of an invariant; and
means, in the integrated cell, for periodically recalculating said at least one value in volatile memory elements of the integrated cell, for holding the invariant in normal operation of the processor and for detecting an invariant loss consecutive to an occurrence of the disturbance.
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Abstract
A cell for detecting a disturbance capable of affecting the operation of a processor in which it is integrated, including circuitry for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance.
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Citations
15 Claims
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1. An integrated cell for detecting a disturbance capable of affecting operation of a processor, comprising:
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non-volatile storage means, in the integrated cell, for storing at least one value of verification of an invariant; and means, in the integrated cell, for periodically recalculating said at least one value in volatile memory elements of the integrated cell, for holding the invariant in normal operation of the processor and for detecting an invariant loss consecutive to an occurrence of the disturbance. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for detecting a disturbance affecting operation of a processor, the method comprising:
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storing, in a non-volatile memory element of an integrated cell, at least one value of verification of an invariant affected by the disturbance; periodically recalculating the at least one value to obtain a current value; storing, in volatile memory elements of the integrated cell, the invariant in normal operation of the processor; and detecting, in the volatile memory elements of the integrated cell, a loss of the invariant upon an occurrence of the disturbance. - View Dependent Claims (8, 9)
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10. An apparatus for detecting a disturbance affecting operation of a processor, the apparatus comprising:
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a non-volatile memory element in an integrated cell for storing at least one value of verification of an invariant affected by the disturbance; and volatile memory elements in the integrated cell for periodically recalculating the at least one value to obtain a current value, holding the invariant in normal operation of the processor, and detecting a loss of the invariant upon an occurrence of the disturbance. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification