Circuit for and method of determining the location of a defect in an integrated circuit

• US 7,363,560 B1
• Filed: 02/23/2005
• Issued: 04/22/2008
• Est. Priority Date: 10/25/2002
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Mark, David, Fan, Yuezhen
• Primary Examiner(s): Britt; Cynthia
• Assistant Examiner(s): Tabone, Jr.; John J.
• Application Number:
  US11/064,129
• Time in Patent Office: 1,154 Days
• Field of Search: None
• US Class Current: 714/725
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.

Claims

1. A circuit for determining the location of a defect in an integrated circuit, said circuit comprising:

a conductor extending from a first node to a second node;

a test signal driver coupled to said first node of said conductor, said test signal driver receiving a test signal using a first clock signal; and

a plurality of detector circuits coupled to said conductor at a plurality of third nodes between said first node and said second node, said plurality of detector circuits coupled to detect at least one output at said plurality of third nodes using a second clock signal;

wherein a trigger edge of said second clock signal varies from a trigger edge of said first clock signal by a predetermined period.

2. The circuit of claim 1 wherein said test signal driver comprises a register.

3. The circuit of claim 1 wherein said plurality of detectors comprises a plurality of registers.

4. The circuit of claim 3 further comprising a memory coupled to each register of said plurality of registers.

5. The circuit of claim 1 wherein said test signal driver comprises a configurable logic block of a programmable logic device.

6. The circuit of claim 1 wherein said detector circuits are implemented in configurable logic blocks of a programmable logic device.

7. A circuit for determining the location of a defect in an integrated circuit, said circuit comprising:

a plurality of layers having conductors;

a conductor of a layer extending from a first node to a second node;

a plurality of vias each extending through at least one layer to said conductor;

a test signal driver coupled to said conductor, said test signal driver receiving a test signal using a first clock signal; and

a plurality of detector circuits coupled to said plurality of vias, said plurality of detector circuits receiving an output of said test signal driver using a second clock signal;

wherein a trigger edge of said second clock signal varies from a trigger edge of said first clock signal by a predetermined period.

8. The circuit of claim 7 wherein said test signal driver comprises a register implemented in a configurable logic block of a programmable logic device.

9. The circuit of claim 7 wherein said plurality of detector circuits comprises registers implemented in configurable logic blocks of a programmable logic device.

10. A method of determining the location of a defect in an integrated circuit, said method comprising the steps of:

coupling an input signal using a first clock signal to a conductor extending between a first node and a second node;

detecting a signal at a detector coupled to said conductor using a second clock signal;

varying a trigger edge of said second clock signal with respect to a trigger edge of said first clock signal; and

determining the location of a defect in said conductor.

11. The method of claim 10 wherein said step of detecting a signal at a detector comprises simultaneously detecting a signal at a plurality of detectors.

12. The method of claim 10 wherein said step of coupling an input signal comprises sequentially coupling an input signal to a test signal driver circuit of a plurality of test signal driver circuits.

13. The method of claim 10 further comprising a step of implementing said detector in a configuration logic block of a configurable logic device.

14. The method of claim 10 wherein said step of varying a trigger edge of said second clock signal with respect to a trigger edge of said first clock signal comprises a step of periodically varying the difference between a trigger edge of said first clock signal and a trigger edge of said second clock signal until a minimum threshold difference has been reached.

15. The method of claim 10 further comprising a step of coupling a plurality of detectors to a plurality of nodes by way of a plurality of vias.

16. The method of claim 15 further comprising a step of determining the location of a via having a defect.

17. The method of claim 15 further comprising a step of mapping the locations of defective vias associated with a given layer.

18. The method of claim 17 further comprising a step of determining an average resistance of a plurality of vias in said integrated circuit.