Circuit for and method of determining the location of a defect in an integrated circuit
First Claim
1. A circuit for determining the location of a defect in an integrated circuit, said circuit comprising:
- a conductor extending from a first node to a second node;
a test signal driver coupled to said first node of said conductor, said test signal driver receiving a test signal using a first clock signal; and
a plurality of detector circuits coupled to said conductor at a plurality of third nodes between said first node and said second node, said plurality of detector circuits coupled to detect at least one output at said plurality of third nodes using a second clock signal;
wherein a trigger edge of said second clock signal varies from a trigger edge of said first clock signal by a predetermined period.
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Abstract
According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.
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Citations
18 Claims
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1. A circuit for determining the location of a defect in an integrated circuit, said circuit comprising:
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a conductor extending from a first node to a second node; a test signal driver coupled to said first node of said conductor, said test signal driver receiving a test signal using a first clock signal; and a plurality of detector circuits coupled to said conductor at a plurality of third nodes between said first node and said second node, said plurality of detector circuits coupled to detect at least one output at said plurality of third nodes using a second clock signal; wherein a trigger edge of said second clock signal varies from a trigger edge of said first clock signal by a predetermined period. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A circuit for determining the location of a defect in an integrated circuit, said circuit comprising:
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a plurality of layers having conductors; a conductor of a layer extending from a first node to a second node; a plurality of vias each extending through at least one layer to said conductor; a test signal driver coupled to said conductor, said test signal driver receiving a test signal using a first clock signal; and a plurality of detector circuits coupled to said plurality of vias, said plurality of detector circuits receiving an output of said test signal driver using a second clock signal; wherein a trigger edge of said second clock signal varies from a trigger edge of said first clock signal by a predetermined period. - View Dependent Claims (8, 9)
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10. A method of determining the location of a defect in an integrated circuit, said method comprising the steps of:
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coupling an input signal using a first clock signal to a conductor extending between a first node and a second node; detecting a signal at a detector coupled to said conductor using a second clock signal; varying a trigger edge of said second clock signal with respect to a trigger edge of said first clock signal; and determining the location of a defect in said conductor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification