Anhydrous HF release of process for MEMS devices

• US 7,365,016 B2
• Filed: 12/22/2005
• Issued: 04/29/2008
• Est. Priority Date: 12/27/2004
• Status: Active Grant

• Current Assignee: Teledyne Digital Imaging, Inc. (Teledyne Technologies Incorporated)
• Original Assignee: Dalsa Incorporated (Teledyne Technologies Incorporated)
• Inventors: Li, Jun, Migneault, Ghislain, Ouellet, Luc
• Primary Examiner(s): Tran; Binh X.
• Application Number:
  US11/314,535
• Publication Number:
  US 20060211163A1
• Time in Patent Office: 859 Days
• Field of Search: 438/704, 438/706, 438/723, 438/724, 216/73, 216/74
• US Class Current: 438/706
• CPC Class Codes: B81C 1/00476 removing a sacrificial layer B81C1/00912 takes precedence
• CPC Class Codes: B81C 1/00936 Releasing the movable structure without liquid etchant
• CPC Class Codes: B81C 2201/0132 Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
• CPC Class Codes: H01L 21/31116 by dry-etching

Abstract

A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.

Claims

1. A method of making a MEMS device containing mechanical parts, comprising:

etching away a sacrificial oxide layer covering an etch-stop silicon nitride underlayer to release said mechanical parts, which are formed on said sacrificial oxide layer, by exposing the sacrificial oxide layer to anhydrous HF at a temperature of less than about 100°

C. and/or at a vacuum level greater than 40 Torr, said etching away of said sacrificial oxide layer on said silicon nitride layer leaving fluorine-containing ammonium etch byproducts resulting from said anhydrous HF attacking said underlying silicon nitride layer; and

subsequently subjecting said etch by-products to a temperature of more than about 100°

C. and at vacuum level lower than 40 Torr without exposure to ambient air to perform an in-situ vacuum sublimation of said etch by-products.

2. A method as claimed in claim 1, wherein the etch by-products comprise a chemical compound containing silicon, nitrogen, fluorine and hydrogen.

3. A method as claimed in claim 1, which is performed on wafers in a batch release process.

4. A method as claimed in claim 3, wherein said batch release process is implemented in a cluster tool.

5. A method as claimed in claim 1, wherein said in-situ sublimation of the etch by-products follows an in-situ decomposition thereof.

6. A method as claimed in claim 5, wherein the etch by-products comprise ammonium fluorosilicate, (NH₄)₂SiF₆, and the in-situ thermal decomposition of ammonium fluorosilicate, (NH₄)₂SiF₆, results in the in-situ sublimation of silicon tetrafluoride, SiF₄(g)↑

, ammonia, NH₃(g)↑

, and ammonium bifluoride, NH₄HF₂↑

.

7. A method as claimed in claim 6, wherein the in-situ sublimation of ammonium bifluoride, NH₄HF₂↑

, at a temperature of at least 100°

C. is performed at a pressure lower than the critical pressure of ammonium bifluoride, NH₄HF₂↑

, at 100°

C.

8. A method as claimed in claim 7, wherein in-situ sublimation of pressure of ammonium bifluoride, NH₄HF₂↑

, is less than 40 Torr.

9. A method as claimed in claim 1, wherein the micro-electro-mechanical system integrates moving mechanical pans, digital and/or analog CMOS control logic and/or CMOS drivers capable of performing actuation functions.

10. A method as claimed in claim 9, wherein providing metal interconnects for the digital and/or analog CMOS control logic and/or CMOS drivers.

11. A method as claimed in claim 10, wherein the metal interconnects are selected from the group consisting of:

aluminum, aluminum alloys, aluminium compounds, titanium, titanium alloys, titanium compounds, copper, gold, tungsten, tungsten alloys, tungsten compounds, molybdenum, molybdenum alloys, molybdenum compounds, and combinations thereof.

12. A method as claimed in claim 1, wherein said etching away is performed in the presence of an organic volatile additive.

13. A method as claimed in claim 12, wherein the organic volatile additive is selected from the group consisting of:

methanol, acetone, 1-buthanol, 2-buthanol, I-propanol, 2-propanol and combinations thereof.

14. A method as claimed in claim 12, wherein the etch by-products result from the exposure of the etch-stop silicon nitride underlayer to anhydrous HF.

15. A method as claimed in claim 12, wherein the in-situ sublimation of the etch by-products follows an in-situ thermal decomposition.

16. A method as claimed in claim 12, which is performed on wafers in a batch release process.

17. A method as claimed in claim 12, wherein said batch release process is implemented in a cluster tool.

18. A method as claimed in claim 12, wherein the etch by-products comprise ammonium fluorosilicate, an in-situ thermal decomposition of ammonium fluorosilicate, (NH₄)₂SiF₆, results in the in-situ sublimation of silicon tetrafluoride, SiF₄(g)↑

, ammonia, NH₃(g)↑

, and ammonium bifluoride, NH₄HF₂↑

, and the in-situ thermal decomposition temperature of ammonium fluorosilicate, (NH₄)₂SiF₆, and the in-situ sublimation temperature of ammonium bifluoride, NH₄HF₂↑

, are at least 100°

C.

19. A method as claimed in claim 18, wherein the in-situ sublimation of ammonium bifluoride, NH₄HF₂↑

, at a temperature of at least 100°

C. is performed at a pressure lower than the critical pressure of ammonium bifluoride, NH₄HF₂↑

, at 100°

C.

20. A method as claimed in claim 19, wherein the in-situ sublimation of pressure of ammonium bifluoride, NH₄HF₂↑

, is lower than about 40 Torr.

21. A method as claimed in claim 12, wherein the sacrificial etch is used to fabricate a micro-electro-mechanical system integrating moving mechanical pans, digital and/or analog CMOS control logic and/or CMOS drivers capable of performing actuation functions.

22. A method as claimed in claim 21, wherein metal interconnects are provided for the digital and/or analog CMOS control logic and/or CMOS drivers.

23. A method as claimed in claim 22, wherein the metal interconnects are selected from the group consisting of:

aluminum, aluminum alloys, aluminium compounds, titanium, titanium alloys, titanium compounds, copper, gold, tungsten, tungsten alloys, tungsten compounds, molybdenum, molybdenum alloys, molybdenum compounds, and combinations of thereof.