Test structure design for reliability test

• US 7,365,529 B2
• Filed: 08/18/2006
• Issued: 04/29/2008
• Est. Priority Date: 11/24/2004
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Yoshida, Naomi, Nagata, Toshiyuki
• Primary Examiner(s): Nguyen; Ha Tran
• Assistant Examiner(s): Nguyen; Tung X.
• Application Number:
  US11/465,646
• Publication Number:
  US 20070013363A1
• Time in Patent Office: 620 Days
• Field of Search: 324/760, 324/765, 324/158.1, 324/716, 324/537, 257/48, 257/767, 257773-776, 257/920, 438/17, 438/468
• US Class Current: 324/750.03
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

Claims

1. A method for evaluating parameters of a semiconductor design, comprising:

generating a semiconductor test structure with at least one conductive line formed in a first metal layer coupled with a plurality of thermal stress-inducing conductive test pads in a second metal layer by a plurality of conductive vias;

taking and recording one or more baseline resistance measurements across at least one of the vias or at least one section of the at least one conductive line;

exposing the test structure to one or more elevated temperatures to generate thermal stress on the test structure;

taking and recording one or more stressed resistance measurements across at least one of the vias or at least one section of the at least one conductive line after exposing the test structure to the one or more elevated temperatures; and

comparing the stressed resistance measurements to the baseline resistance measurements in order to detect voids formed in at least one of the conductive line or the vias.

2. The method of claim 1, wherein dimensions of the test pads are selected to simulate wire lengths that may be used in the second metal layer in a final design.

3. The method of claim 1, wherein dimensions of at least two of the test pads are different.

4. The method of claim 1, wherein the test structure also comprises test pads in a third metal layer coupled to the conductive line by vias, wherein the first metal layer is between the second and third metal layers.

5. The method of claim 1, further comprising forming dummy lines in the first metal layer adjacent the conductive line, wherein the dummy lines are not coupled to the test pads.

6. The method of claim 1, further comprising:

forming probe contact pads electrically coupled to the first conductive line at different locations; and

wherein taking the resistance measurements comprises taking four-terminal resistance measurements by supplying a current via two of the probe contact pads and measuring a potential voltage across a different two of the probe contact pads.

7. The method of claim 1, further comprising generating a set of recommended design parameter combinations based on the results of comparing the stressed resistance measurements to the baseline resistance measurements.