Contention-free keeper circuit and a method for contention elimination

• US 7,365,587 B2
• Filed: 04/07/2006
• Issued: 04/29/2008
• Est. Priority Date: 04/07/2006
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kenkare, Prashant U., Ramaraju, Ravindraraj
• Primary Examiner(s): Cox; Cassandra
• Application Number:
  US11/279,018
• Publication Number:
  US 20070236263A1
• Time in Patent Office: 753 Days
• Field of Search: None
• US Class Current: 327/331
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356147 using pass gates
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a high-to-low contention element coupled between the first node and a first supply, and coupled to the delay element output. The contention-free keeper circuit may further include a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit.

Claims

1. A contention-free keeper circuit, comprising:

a keeper circuit, wherein the keeper circuit includes a first node and a second node;

a delay element for providing a time delay, the delay element having an input and an output, wherein the delay element input is coupled to one selected from the group consisting of the first node and the second node;

a high-to-low contention elimination element coupled between the first node and a first supply, and coupled to the delay element output; and

a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit, further wherein the first supply is greater than the second supply.

2. The circuit of claim 1, wherein the time delay is at least equal to or greater than a time duration of one selected from the low-to-high signal transition and the high-to-low signal transition.

3. The circuit of claim 2, further wherein the time duration comprises a longer of (i) the low-to-high signal transition duration or (ii) the high-to-low signal transition duration.

4. The circuit of claim 1, wherein the delay element comprises an inverting delay element and wherein the delay element input is coupled to the second node.

5. The circuit of claim 1, wherein the delay element comprises a non-inverting delay element and wherein the delay element is coupled to the first node.

6. The circuit of claim 1, wherein the delay element comprises an odd number of serially coupled inverting elements.

7. The circuit of claim 1, wherein the delay element comprises a plurality of delay elements and a multiplexer, the plurality of delay elements having one or more different time delay durations, the multiplexer having a plurality of inputs and an output, each delay element of the plurality being coupled between (i) one of the first node or second node and (ii) a corresponding input of the multiplexer, and the output of the multiplexer being coupled to a third node, wherein responsive to a select input, the multiplexer couples a corresponding delay element of the plurality to the third node.

8. The circuit of claim 7, wherein the plurality of delay elements comprise inverting delay elements.

9. The circuit of claim 1, wherein the high-to-low contention elimination element comprises a first type transistor, and wherein the low-to-high contention elimination element comprises a second type transistor different from the first type transistor.

10. The circuit of claim 9, further wherein the first type transistor includes a PMOS transistor, and wherein the second type transistor includes an NMOS transistor.

11. The circuit of claim 1, wherein the keeper circuit includes an inverter coupled between the first node and the second node.

12. The circuit of claim 1, wherein the low-to-high transition element includes a transistor of a first type and wherein the high-to-low transition element includes a transistor of a second type, the second type being different from the first type.

13. In a signal line having inherent resistance and inherent capacitance, the signal line includes a contention-free keeper circuit according to claim 1, wherein the contention-free keeper circuit is coupled to the signal line in one selected from the group consisting of a parallel configuration, a serial configuration, and a termination configuration.

14. In a memory array having a plurality of bit cells, the memory array including a contention-free keeper circuit according to claim 1, wherein the contention-free keeper circuit is coupled to a word line of the memory array of bit cells in one selected from the group consisting of a parallel configuration, a serial configuration, and a termination configuration.

15. A contention-free keeper circuit, comprising:

a keeper circuit, wherein the keeper circuit includes a first node and a second node;

a delay element for providing a time delay, the delay element having an input and an output, wherein the delay element input is coupled to one selected from the group consisting of the first node and the second node; and

a contention elimination element coupled between a supply and the first node, and coupled to the delay element output, wherein responsive to a transition at the first node from a first level to another level and the time delay, the contention elimination element eliminates a contention within the keeper circuit.

16. The contention-free keeper circuit of claim 15, wherein the transition is a low-to-high signal transition or a high-to-low signal transition.

17. The contention-free keeper circuit of claim 16, wherein the time delay is at least equal to or greater than a time duration of one selected from the low-to-high signal transition and the high-to-low signal transition.

18. The contention-free keeper circuit of claim 15 wherein the delay element comprises an odd number of serially coupled inverting elements.

19. The contention-free keeper circuit of claim 15, wherein the delay element comprises an inverting delay element and wherein the delay element input is coupled to the second node.

20. The contention-free keeper circuit of claim 15, wherein the delay element comprises a plurality of delay elements and a multiplexer, the plurality of delay elements having one or more different time delay durations, the multiplexer having a plurality of inputs and an output, each delay element of the plurality being coupled between (i) one of the first node or second node and (ii) a corresponding input of the multiplexer, and the output of the multiplexer being coupled to a third node, wherein responsive to a select input, the multiplexer couples a corresponding delay element of the plurality to the third node.