Multilevel power amplifier architecture using multi-tap transformer

• US 7,365,602 B2
• Filed: 10/26/2006
• Issued: 04/29/2008
• Est. Priority Date: 10/28/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bhatti, Iqbal, Castaneda, Jesus
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): NGUYEN, HIEU P
• Application Number:
  US11/553,190
• Publication Number:
  US 20070069818A1
• Time in Patent Office: 551 Days
• Field of Search: 330/295, 330/195, 330/301, 330/276, 330/286
• US Class Current: 330/295
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers

Abstract

A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

Claims

1. A power amplifier system, comprising:

a multi-tap integrated circuit transformer coupled to a shared output load, where the transformer comprises N input taps to provide N different impedance levels to the shared output load; and

a plurality of N power amplifier coupled respectively to each of the N input taps, whereby any combination of the N power amplifiers can be turned on at once and still maintain a power efficiency regardless of which power amplifiers are turned on.

2. The power amplifier system of claim 1, where each power amplifier comprises:

an input transistor having a gate, a source, and a drain, wherein the gate is operably coupled to receive an input signal, and wherein the source is coupled to a first DC voltage potential;

an inductor operably coupled between a second DC voltage potential and the drain of the input transistor, where the drain of the input transistor is operably coupled to an input tap of the transformer to provide the output signal from the power amplifier to the transformer.

3. The power amplifier system of claim 1, wherein an input signal to a power amplifier is coupled through an input tap of the transformer to the shared output load to provide on-chip impedance matching between the power amplifier and the shared output load.

4. The power amplifier system of claim 1, wherein each of the plurality of N power amplifiers comprises a differential power amplifier.

5. The power amplifier system of claim 1, wherein each of the plurality of N power amplifiers comprises a single ended amplifier.

6. The power amplifier system of claim 1, where the shared output load comprises an antenna.

7. The power amplifier system of claim 1, where the multi-tap integrated circuit transformer comprises a secondary winding and a primary winding, where the primary winding is operably coupled to the shared output load, and where the secondary winding comprises N input taps, where each tap is operably coupled to receive an output signal from one of the plurality of N power amplifiers.

8. The power amplifier system of claim 1, wherein the plurality of N power amplifiers and the multi-tap integrated circuit transformer are integrated on a single integrated circuit.

9. A multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, comprising:

a primary winding formed on a first layer of an integrated circuit and operably coupled to a shared output impedance;

a secondary winding formed on a second layer of the integrated circuit, said secondary winding comprising a plurality of input taps, where each input tap is operably coupled to receive an output signal from one of a plurality of power amplifiers, any combination of which can be turned on at once, such that each input tap provides a different impedance level to thereby maintain a power output efficiency for the transformer across multiple power levels.

10. The multi-tap transformer of claim 9, where the shared output impedance comprises an antenna.

11. The multi-tap transformer of claim 9, where the plurality of input taps comprises a first set of input taps for receiving a first differential input signal and a second set of input taps for receiving a second differential input signal.

12. The multi-tap transformer of claim 9, where the plurality of input taps comprises a reference input tap coupled to a reference potential, a first input tap for receiving a first single-ended input signal and a second input tap for receiving a second single-ended input signal.

13. The multi-tap transformer of claim 9, where the secondary winding comprises a common node, a first portion and a second portion, where each portion has one node, a first tap and a second tap.

14. The multi-tap transformer of claim 13, where the common node is operably coupled to a reference potential, the nodes from the first and second portions are operably coupled to receive a first differential input signal, the first taps of the first and second portions are operably coupled to receive a second differential input signal, and the second taps of the first and second portions are operably coupled to receive a third differential input signal.

15. The multi-tap transformer of claim 9, where the secondary winding has a generally octagonal geometric shape.

16. The multi-tap transformer of claim 9, where the secondary winding comprises a common node, a first portion and a second portion, where each portion has one node and multiple taps.

17. A method for delivering power to an output impedance through a multi-tap transformer, comprising:

selectively coupling a plurality of power amplifiers to a corresponding plurality of multi-tap transformer inputs on a multi-tap transformer that is coupled to an output impedance, where each multi-tap transformer input provides a predetermined load impedance for the power amplifier that is coupled to said multi-tap transformer input, thereby providing a variable load impedance for maintaining a power efficiency while output power levels vary at the output impedance.

18. The method of claim 17 implemented on a single CMOS integrated circuit wireless communications device.

19. The method of claim 17, further comprising supplying a differential input signal as an input to one or more of the power amplifiers.

20. The method of claim 17, further comprising supplying a single-ended input signal as an input to one or more of the power amplifiers.