Integrated clock generator and timing/frequency reference

• US 7,365,614 B2
• Filed: 03/20/2006
• Issued: 04/29/2008
• Est. Priority Date: 03/22/2004
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Mobius Microsystems, Inc. (Renesas Electronics Corporation)
• Inventors: McCorquodale, Michael Shannon, Pernia, Scott Michael, Kubba, Sundus, O'Day, Justin, Carichner, Gordon
• Primary Examiner(s): Mis; David
• Application Number:
  US11/384,758
• Publication Number:
  US 20060152293A1
• Time in Patent Office: 771 Days
• Field of Search: 331/1.A, 331/2, 331/8, 331/10, 331/11, 331 16- 18, 331/25, 331/36.C, 331/36.L, 331/57, 331/117.R, 331/117.FE, 331/117.D, 331/173, 331/175, 331/177.R, 331/177.V, 331/179, 331/DIG.2
• US Class Current: 331/179
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 5/06 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03B 5/1203 the amplifier being a single transistor
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1218 the generator being of the balanced type
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1253 the transistors being field-effect transistors
• CPC Class Codes: H03B 5/1256 the means comprising a variable inductance
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03J 1/0008 using a central processing unit, e.g. a microprocessor digital tuning in general H03J5/0245
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

In various embodiments, the invention provides a clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

Claims

1. An integrated circuit, the integrated circuit comprising:

a resonator comprising an inductor and a capacitor, the resonator adapted to provide a first reference signal having a first frequency;

a voltage controller adapted to provide a plurality of voltage control signals;

a plurality of switchable, controlled reactance modules coupled to the resonator and to the voltage controller, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to a corresponding voltage control signal of the plurality of voltage control signals to modify the first frequency; and

a processor operatively coupled to the resonator.

2. The integrated circuit of claim 1, further comprising:

a divider circuit coupled to the resonator, the divider circuit adapted to provide a second reference signal having a second frequency; and

wherein the processor is coupled through the divider to the resonator, and is adapted to receive the second reference signal.

3. The integrated circuit of claim 1, further comprising:

a locking circuit coupled to the resonator, the locking circuit adapted to lock to the first reference signal and provide a second reference signal having a second frequency which is a rational multiple of the first frequency, wherein the locking circuit is at least one of the following locking circuits;

a phase-locked loop, a delay-locked loop, or an injection locking circuit; and

wherein the processor is coupled through the locking circuit to the resonator, and is adapted to receive the second reference signal.

4. The integrated circuit of claim 1, wherein the processor is any type of circuitry adapted to perform a function.

5. The integrated circuit of claim 1, wherein the processor is at least one of the following types of processors:

a microprocessor;

a digital signal processor;

a controller;

a microcontroller;

a universal serial bus (USB) controller;

a Peripheral Component Interconnect (PCI) controller;

a Peripheral Component Interconnect Express (PCI-e) controller;

a Firewire controller;

an AT Attachment (ATA) interface controller, an Integrated Drive Electronics (IDE) controller;

a Small Computer Systems Interface (SCSI) controller;

a television controller;

a local area network (LAN) controller;

an Ethernet controller;

a video controller;

an audio controller;

a modem processor;

an MPEG controller;

a multimedia controller;

a communication controller;

a mobile communication controller;

an IEEE 802.11 controller;

a GSM controller;

a GPRS controller;

a PCS controller;

an AMPS controller;

a CDMA controller;

a WCDMA controller;

a spread spectrum controller;

a wireless LAN controller;

an IEEE 802.11 controller;

a DSL controller;

a T1 controller;

a ISDN controller;

or a cable modem controller.

6. The integrated circuit of claim 1, further comprising:

a memory coupled to the processor and further coupled to the locking circuit to receive the second reference signal; and

an input/output interface coupled to the processor and further coupled to the locking circuit to receive the second reference signal.

7. The integrated circuit of claim 1, further comprising:

a plurality of dividers or locking circuits coupled to the resonator, the plurality of dividers or locking circuits adapted to provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies.

8. The integrated circuit of claim 7, further comprising:

control circuitry coupled to the plurality of dividers or locking circuits, the control circuitry adapted to provide a control signal to the plurality of dividers or locking circuits to modify a divide ratio to provide a spread-spectrum second reference signal of the plurality of plurality of second reference signals.

9. The integrated circuit of claim 7, further comprising:

control circuitry coupled to the plurality of switchable, controlled reactance modules, the control circuitry adapted to provide a control signal to the plurality of switchable, controlled reactance modules to selectively switch the plurality of switchable, controlled reactance modules to modify the first frequency to provide a spread-spectrum first reference signal.

10. The integrated circuit of claim 7, further comprising:

switching circuitry coupled to the plurality of dividers or locking circuits and to the processor, the switching circuitry adapted to selectively couple the processor to the plurality of dividers or locking circuits by switching a selected, second reference signal of the corresponding plurality of second reference signals to the processor.

11. The integrated circuit of claim 10, further comprising:

control circuitry coupled to the switching circuitry, the control circuitry adapted to provide a control signal to the switching circuitry to switch the selected, second reference signal to the processor.

12. The integrated circuit of claim 10, further comprising:

a coefficient register coupled to the switching circuitry, the coefficient register adapted to provide a control coefficient to the switching circuitry to switch the selected, second reference signal to the processor.

13. The integrated circuit of claim 7, wherein each divider of the plurality of dividers or locking circuits further comprises a plurality of asynchronous or synchronous divider circuits, and wherein the plurality of corresponding frequencies are determined by corresponding divide ratios of the plurality of divider circuits.

14. The integrated circuit of claim 1, wherein the resonator, voltage controller, and plurality of switchable, controlled reactance modules are embodied in a first integrated circuit, and wherein the processor is embodied in a second integrated circuit, and wherein the second integrated circuit is coupled through a plurality of bonding wires to the first integrated circuit.

15. The integrated circuit of claim 1, wherein the resonator is configured to have at least one of the following configurations:

a double-balanced, differential LC configuration;

a differential n-MOS cross-coupled topology;

a differential p-MOS cross-coupled topology;

a single-ended Colpitts LC configuration;

a single-ended Hartley LC configuration;

a differential, common base Colpitts LC configuration;

a differential, common collector Colpitts LC configuration;

a differential, common base Hartley LC configuration;

a differential, common collector Hartley LC configuration;

a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

16. The integrated circuit of claim 1, wherein the inductor is an active inductor comprising a plurality of transistors or is a passive inductor comprising a CMOS-compatible conductive layer.

17. The integrated circuit of claim 1, further comprising:

a coefficient register coupled to the plurality of switchable, controlled reactance modules, the coefficient register adapted to store a plurality of coefficients and to provide a corresponding coefficient to control switching of a corresponding controlled reactance module to the resonator.

18. The integrated circuit of claim 17, wherein the plurality of switchable, controlled reactance modules further comprise:

a plurality of switches coupled to the coefficient register; and

a plurality of variable capacitors correspondingly coupled to the plurality of switches and to the voltage controller, the plurality of variable capacitors adapted to provide a selected capacitance in response to a corresponding control voltage.

19. The integrated circuit of claim 18, wherein the plurality of switchable, controlled reactance modules further comprise:

a plurality of fixed capacitors correspondingly coupled to the plurality of switches, the plurality of fixed capacitors adapted to provide a selected capacitance in response to a corresponding coefficient.

20. The integrated circuit of claim 19, wherein the plurality of coefficients are determined post-fabrication by calibration to a second reference frequency signal.

21. The integrated circuit of claim 1, further comprising:

a transconductance amplifier coupled to the resonator, the transconductance amplifier comprising a variable current source, the variable current source adapted to provide a corresponding current in response to ambient or operating temperature.

22. An apparatus comprising:

a harmonic oscillator comprising an inductor and a capacitor, the harmonic oscillator adapted to provide a first reference signal having a first frequency;

a plurality of resistive modules adapted to generate a plurality of voltage control signals;

a plurality of controlled reactance modules coupled to the harmonic oscillator and to the plurality of resistive modules, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to a corresponding voltage control signal of the plurality of voltage control signals to modify the first frequency;

a first coefficient register coupled to the plurality of switches, the first coefficient register adapted to store a first plurality of switching coefficients;

a first plurality of switches coupled to the plurality of resistive modules and to the plurality of controlled reactance modules, each switch of the first plurality of switches responsive to a corresponding switching coefficient of the first plurality of switching coefficients to couple a selected control voltage of the plurality of control voltages to a corresponding controlled reactance module; and

a processor operatively coupled to the harmonic oscillator to receive the first reference signal.

23. The apparatus of claim 22, further comprising:

a locking circuit coupled to the harmonic oscillator, the locking circuit adapted to lock to the first reference signal and provide a second reference signal having a second frequency which is a rational multiple of the first frequency; and

wherein the processor is coupled through the locking circuit to the harmonic oscillator, and is adapted to receive the second reference signal.

24. The apparatus of claim 23, wherein the locking circuit is at least one of the following locking circuits:

a phase-locked loop, a delay-locked loop, or an injection locking circuit.

25. The apparatus of claim 22, wherein the processor is any type of circuitry adapted to perform a function.

26. The apparatus of claim 22, wherein the processor is at least one of the following types of processors:

a microprocessor;

a digital signal processor;

a controller;

a microcontroller;

a universal serial bus (USB) controller;

a Peripheral Component Interconnect (PCI) controller;

a Peripheral Component Interconnect Express (PCI-e) controller;

a Firewire controller;

an AT Attachment (ATA) interface controller, an Integrated Drive Electronics (IDE) controller;

a Small Computer Systems Interface (SCSI) controller;

a television controller;

a local area network (LAN) controller;

an Ethernet controller;

a video controller;

an audio controller;

a modem processor;

an MPEG controller;

a multimedia controller;

a communication controller;

a mobile communication controller;

an IEEE 802.11 controller;

a GSM controller;

a GPRS controller;

a PCS controller;

an AMPS controller;

a CDMA controller;

a WCDMA controller;

a spread spectrum controller;

a wireless LAN controller;

an IEEE 802.11 controller;

a DSL controller;

a T1 controller;

a ISDN controller;

or a cable modem controller.

27. The apparatus of claim 22, further comprising:

a memory coupled to the processor and further coupled to the locking circuit to receive the second reference signal; and

an input/output interface coupled to the processor and further coupled to the locking circuit to receive the second reference signal.

28. The apparatus of claim 22, further comprising:

a plurality of dividers or locking circuits coupled to the harmonic oscillator, the plurality of dividers or locking circuits adapted to provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies.

29. The apparatus of claim 28, further comprising:

a second plurality of switches coupled to the plurality of dividers or locking circuits and to the processor, the second plurality of switches adapted to selectively couple the processor to the plurality of dividers or locking circuits by switching a selected, second reference signal of the corresponding plurality of second reference signals to the processor.

30. The apparatus of claim 29, further comprising:

control circuitry coupled to the second plurality of switches, the control circuitry adapted to provide a control signal to the second plurality of switches to switch the selected, second reference signal to the processor.

31. The apparatus of claim 29, further comprising:

a second coefficient register coupled to the second plurality of switches, the second coefficient register adapted to provide a control coefficient to the second plurality of switches to switch the selected, second reference signal to the processor.

32. The apparatus of claim 28, wherein each divider of the plurality of dividers or locking circuits further comprises a plurality of asynchronous or synchronous divider circuits, and wherein the plurality of corresponding frequencies are determined by corresponding divide ratios of the plurality of divider circuits.

33. The apparatus of claim 22, wherein the apparatus is embodied as a single integrated circuit.

34. The apparatus of claim 22, wherein the apparatus is embodied as a first integrated circuit coupled through a plurality of bonding wires to a second integrated circuit.

35. The integrated circuit of claim 22, wherein the first plurality of switches are further responsive to a corresponding switching coefficient of the first plurality of switching coefficients to couple a corresponding controlled reactance module of the plurality of controlled reactance modules to the harmonic oscillator to modify the first frequency.

36. The integrated circuit of claim 22, wherein the harmonic oscillator has at least one configuration of the following configurations:

a double-balanced, differential LC configuration;

a differential n-MOS cross-coupled topology;

a differential p-MOS cross-coupled topology;

a single-ended Colpitts LC configuration;

a single-ended Hartley LC configuration;

a differential, common base Colpitts LC configuration;

a differential, common collector Colpitts LC configuration;

a differential, common base Hartley LC configuration;

a differential, common collector Hartley LC configuration;

a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

37. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise:

a plurality of variable capacitors correspondingly coupled to the plurality of switches and to the voltage controller, the plurality of variable capacitors adapted to provide a selected capacitance in response to a corresponding control voltage; and

a plurality of fixed capacitors correspondingly coupled to the plurality of switches, the plurality of fixed capacitors adapted to provide a selected capacitance in response to a corresponding switching coefficient.

38. The integrated circuit of claim 22, wherein at least one control voltage of the plurality of control voltages is responsive to a parameter of a plurality of parameters, wherein the plurality of parameters are variable and comprise at least one of the following parameters:

temperature, fabrication process, voltage, age, and frequency.

39. The integrated circuit of claim 38, further comprising:

a current source coupled to the plurality of resistive modules, the current source adapted to provide a parameter-dependent current to at least one resistive module of the plurality of resistive modules to generate at least one control voltage, of the plurality of control voltages, which is parameter-dependent.

40. The integrated circuit of claim 39, wherein the current source has at least one complementary to absolute temperature (CTAT) configuration, proportional to absolute temperature (PTAT) configuration, or proportional to absolute temperature squared (PTAT²) configuration.

41. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise a plurality of differently-weighted fixed capacitances and variable capacitances, and wherein the plurality of switches are responsive to the plurality of switching coefficients to couple a fixed capacitance to the harmonic oscillator and to couple a first control voltage of the plurality of control voltages to a variable capacitance coupled to the harmonic oscillator.

42. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise:

a plurality of differently-weighted switchable capacitive modules coupled to the coefficient register and to the harmonic oscillator, each switchable capacitive module having a first fixed capacitance and a second fixed capacitance, each switchable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between the first fixed capacitance and the second fixed capacitance.

43. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise:

at least one switchable variable capacitive module coupled to the coefficient register and to the harmonic oscillator, the at least one switchable variable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch between a first voltage and a second voltage of a plurality of control voltages.

44. The integrated circuit of claim 22, wherein the plurality of controlled reactance modules further comprise:

a plurality of switchable variable capacitive modules coupled to the coefficient register and to the harmonic oscillator, each switchable variable capacitive module responsive to a corresponding coefficient of the plurality of coefficients to switch to a selected control voltage of a plurality of control voltages, the plurality of control voltages comprising a plurality of different magnitude voltages, and wherein the selected control voltage is substantially constant over temperature variations.

45. An integrated circuit comprising:

a resonator comprising an inductor and a capacitor, the resonator adapted to provide a first reference signal having a first frequency;

a sensor adapted to provide a second signal in response to operating temperature or fabrication process variation;

a voltage controller adapted to provide a plurality of voltage control signals;

a plurality of switchable, controlled reactance modules coupled to the resonator and to the voltage controller, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to a corresponding voltage control signal of the plurality of voltage control signals to modify the first frequency;

a plurality of dividers operatively coupled to the resonator, the plurality of dividers adapted to provide a corresponding plurality of second reference signals having a plurality of corresponding frequencies; and

a processor adapted to receive a selected, second reference signal of the plurality of second reference signals.

46. The integrated circuit of claim 45, further comprising:

switching circuitry coupled to the plurality of dividers and to the processor, the switching circuitry adapted to switch the selected, second reference signal to the processor.

47. The integrated circuit of claim 45, further comprising:

at least one locking circuit coupled to the resonator and to the processor, wherein the locking circuit is at least one of the following locking circuits;

a phase-locked loop, a delay-locked loop, or an injection locking circuit.

48. The integrated circuit of claim 45, wherein the processor is at least one of the following types of processors:

a microprocessor;

a digital signal processor;

a controller;

a microcontroller;

a universal serial bus (USB) controller;

a Peripheral Component Interconnect (PCI) controller;

a Peripheral Component Interconnect Express (PCI-e) controller;

a Firewire controller;

an AT Attachment (ATA) interface controller, an Integrated Drive Electronics (IDE) controller;

a Small Computer Systems Interface (SCSI) controller;

a television controller;

a local area network (LAN) controller;

an Ethernet controller;

a video controller;

an audio controller;

a modem processor;

an MPEG controller;

a multimedia controller;

a communication controller;

a mobile communication controller;

an IEEE 802.11 controller;

a GSM controller;

a GPRS controller;

a PCS controller;

an AMPS controller;

a CDMA controller;

a WCDMA controller;

a spread spectrum controller;

a wireless LAN controller;

an IEEE 802.11 controller;

a DSL controller;

a T1 controller;

a ISDN controller;

or a cable modem controller.

49. The integrated circuit of claim 45, further comprising:

control circuitry coupled to the switching circuitry, the control circuitry adapted to provide a control signal to the switching circuitry to switch the selected, second reference signal to the processor.

50. The integrated circuit of claim 45, further comprising:

a coefficient register coupled to the switching circuitry, the coefficient register adapted to provide a control coefficient to the switching circuitry to switch the selected, second reference signal to the processor.

51. The integrated circuit of claim 45, wherein the resonator is configured to have at least one of the following configurations:

a double-balanced, differential LC configuration;

a differential n-MOS cross-coupled topology;

a differential p-MOS cross-coupled topology;

a single-ended Colpitts LC configuration;

a single-ended Hartley LC configuration;

a differential, common base Colpitts LC configuration;

a differential, common collector Colpitts LC configuration;

a differential, common base Hartley LC configuration;

a differential, common collector Hartley LC configuration;

a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

52. The integrated circuit of claim 45, further comprising:

a coefficient register coupled to the plurality of switchable, controlled reactance modules, the coefficient register adapted to store a plurality of coefficients and to provide a corresponding coefficient to control switching of a corresponding controlled reactance module to the resonator.