Video and graphics system with a single-port RAM

• US 7,365,752 B2
• Filed: 07/29/2004
• Issued: 04/29/2008
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Xie, Xiaodong
• Primary Examiner(s): Tung; Kee M.
• Assistant Examiner(s): RICHER, JONI
• Application Number:
  US10/901,648
• Publication Number:
  US 20050024369A1
• Time in Patent Office: 1,370 Days
• Field of Search: 345/536, 345/530, 345/560, 345/501, 345/418, 345/531, 345/534, 345/535, 345/547, 345/545, 345/554, 345/541, 345/564, 345/629, 345/619, 348/715, 348/571
• US Class Current: 345/560
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/28 for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/42692 : for reading from or writing on a volatile storage medium, e.g. Random Access Memory [RAM]
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 : of multiple content streams on the same device
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440218 : by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 conversion of standards in analogue television systems H04N7/01
• CPC Class Codes: H04N 21/8146 : involving graphical data, e.g. 3D object, 2D graphics
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Claims

1. A graphics system comprising:

a display engine for receiving and processing graphics data to generate a graphics image;

a graphics filter for converting a format of the graphics image from a first format to a second format when the graphics system operates in a standard definition (SD) mode, but not in a high definition (HD) mode; and

a plurality of line buffers implemented in a single-port RAM, each said line buffer for temporarily storing a line of the graphics image, the line buffers being accessed in an interleaved manner, such that a read operation is performed between a first write operation and a second write operation, wherein the write operations are performed on one said line buffer being pointed to by a pointer when multiple said line buffers are used, and wherein the first and second write operations are performed using two sequential memory locations of the line buffers.

2. The graphics system of claim 1, wherein another read operation is performed immediately after the second write operation, and wherein the read operation and said another read operation are performed using another two sequential memory locations of the line buffers.

3. The graphics system of claim 1, wherein the read and write operations use a same clock or control signals generated using the same clock.

4. The graphics system of claim 1, wherein the read operations have higher priority than the write operations.

5. The graphics system of claim 1, wherein the single-port RAM is an SRAM, an SDRAM or a flash memory device.

6. The graphics system of claim 2, wherein the read operations are performed when addresses for the memory locations are even.

7. A video and graphics system for blending a graphics image with a video, the system comprising:

a display engine for receiving and processing graphics data to generate the graphics image;

a plurality of line buffers implemented in a single-port RAM, each said line buffer for temporarily storing a line of the graphics image, the line buffers being accessed in an interleaved manner, such that a read operation is performed between a first write operation and a second write operation, the write operations being performed on one said line buffer being pointed to by a pointer when multiple said line buffers are used;

a graphics filter suitable for converting a format of the graphics image from a first format to a second format, wherein the graphics filter converts the format of the graphics image when the graphics system operates in a standard definition (SD) mode, but not in a high definition (HD) mode; and

a video compositor for receiving the graphics image and the video and blending the graphics image with the video to generate an image to be displayed, wherein the first and second write operations are performed using two sequential memory locations of the line buffers.

8. The video and graphics system of claim 7, wherein the read and write operations use the same clock or control signals generated using the same clock.