Content addressable memory including main-match lines and sub-match lines

• US 7,366,001 B2
• Filed: 12/23/2004
• Issued: 04/29/2008
• Est. Priority Date: 12/25/2003
• Status: Expired due to Fees

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Hitachi, Ltd., Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Hanzawa, Satoru, Sakata, Takeshi, Kajigaya, Kazuhiko
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US11/019,321
• Publication Number:
  US 20050157526A1
• Time in Patent Office: 1,223 Days
• Field of Search: 365/49, 505/835, 505/839, 711/108, 706/50, 341/104, 341/105, 341/106
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements

Abstract

The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Claims

1. A semiconductor device comprising:

a plurality of bit lines extending in a first direction;

a plurality of search lines extending in the first direction, each said search line being paired with a corresponding one of the bit lines;

a plurality of word lines extending in a second direction orthogonal to the first direction;

a plurality of main-match lines extending in the second direction;

a plurality of sub-match lines extending in the second direction, each said sub-match line being paired with a corresponding one of the main match lines;

a plurality of memory cells arranged at respective crossing points of the plurality of bit lines and the plurality of word lines;

a plurality of sub-match detectors connected to corresponding ones of the sub-match lines; and

a plurality of main-match detectors connected to corresponding ones of the main-match lines;

wherein each said memory cell is connected to a corresponding one of the sub-match lines and is also connected to a corresponding one of the main-match lines through the corresponding sub-match detector,

information inputted through the plurality of search lines and information stored in the memory cells are compared in the memory cells, and

the stored information includes one or more blocks of code, each said block of code having a plurality of bits, and at least one of said bits per block of code has a logic value of ‘

1’

.

2. The semiconductor device according to claim 1, wherein an even number of memory cells are connected to each of the plurality of sub-match lines.

3. The semiconductor device according to claim 2, wherein groups of two memory cells store quaternary information.

4. The semiconductor device according to claim 3, wherein each said memory cell includes:

a first and a second MOS transistor connected between the corresponding sub-match line and a ground electrode to form a current path; and

a memory circuit which stores binary information,

wherein a gate electrode of the first MOS transistor is connected to a corresponding search line and a gate electrode of the second MOS transistor is connected to the memory circuit.

5. The semiconductor device according to claim 4, wherein the memory circuit includes a third MOS transistor and a capacitor, and is subjected to a refresh operation, which includes read and write operations performed periodically.