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Method and apparatus for reducing standby current in a dynamic random access memory during self refresh

  • US 7,366,047 B2
  • Filed: 11/09/2005
  • Issued: 04/29/2008
  • Est. Priority Date: 11/09/2005
  • Status: Expired due to Fees
First Claim
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1. A dynamic random access memory, comprising:

  • a first dynamic random access memory cell;

    a second dynamic random access memory cell to be refreshed;

    a sense amplifier; and

    a control circuit configured to connect the sense amplifier to a first bit line associated with the first dynamic random access memory cell and to a second bit line associated with the second dynamic random access memory cell and to equalize bit line voltages and inputs of the sense amplifier to a bit line equalization voltage during a pre-conditioning time that is prior to a refresh time, wherein the control circuit is configured to isolate the first bit line from the sense amplifier and refresh the second dynamic random access memory cell during the refresh time.

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