Software and hardware simulation

• US 7,366,650 B2
• Filed: 02/22/2002
• Issued: 04/29/2008
• Est. Priority Date: 04/12/2001
• Status: Expired due to Fees

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Bruce, Alistair Crone, Nightingale, Andrew Mark
• Primary Examiner(s): Shah; Kamini
• Assistant Examiner(s): PATEL, SHAMBHAVI K
• Application Number:
  US10/079,811
• Publication Number:
  US 20020152456A1
• Time in Patent Office: 2,258 Days
• Field of Search: 703/26, 703/13, 703/20, 702/2, 702/4, 702/28, 702/118, 714/739, 716/4, 716/5, 716/18
• US Class Current: 703/26
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respective simulators. The response of both the software and the hardware to the simulation conducted can be monitored to check for proper operation.

Claims

1. A method of simulating a system having a software component and a hardware component, said method comprising the steps of:

(i) modelling operation of said software component using a software simulator;

(ii) modelling operation of said hardware component using a hardware simulator;

(iii) linking said hardware simulator and said software simulator to model interaction between said modelled operation of said hardware component and said modelled operation of said software component;

(iv) generating with a test controller, during said modelling of software and hardware components and said interaction, a software stimulus for said software component and a hardware stimulus for said hardware component, said software stimulus and said hardware stimulus are associated so as to permit verification of correct interoperability of said software component and said hardware component, wherein said modelled interaction between said software component and said hardware component proceeds independently of said test controller;

(v) modelling the response of said software component to said software stimulus; and

(vi) modelling the response of said hardware component to said hardware stimulus, wherein said software stimulus is passed to said software simulator by issuing a remote procedure call from said test controller to said software simulator.

2. A method as claimed in claim 1, wherein said test controller issues said remote procedure call by writing call data specifying said software stimulus to a shared memory, said software simulator reading call data from said shared memory to trigger modelling of operation of said software component in response to said software stimulus.

3. A method as claimed in claim 2, wherein said test controller sets a start flag within said shared memory to indicate to said software simulator that said shared memory contains call data specifying a software stimulus to be modelled.

4. A method as claimed in claim 3, wherein said software simulator polls said start flag to determine if there is a software stimulus to be modelled.

5. A method as claimed in claim 3, wherein said software simulator resets said start flag to indicate to said test controller that modelling of said software stimulus has been completed.

6. A method as claimed in claim 2, wherein said call data includes one or more of:

(i) data identifying a software routine to be modelled within said software component; and

(ii) variable data to be used in responding to said software stimulus.

7. A method as claimed in claim 1, wherein said hardware component is a hardware peripheral within a data processing system.

8. A method as claimed in claim 1, wherein said software component is a software driver for said hardware component.

9. A method as claimed in claim 1, further comprising monitoring modelled signals at an interface with said hardware component that are generated in response to simulation of said software component and said hardware component.

10. A method as claimed in claim 9, wherein said modelled signals are monitored for compliance with rules defining permitted values for said modelled signals.

11. A method as claimed in claim 1, wherein said software simulator is monitored to determine coverage of a range of software stimuli that may be applied to said software simulator.

12. A method as claimed in claim 1, wherein said hardware simulator is monitored to determine coverage of a range of hardware stimuli that may be applied to said hardware simulator.

13. A method as claimed in claim 1, wherein said software simulator is an instruction set simulator that serves to model execution of software program instruction by a data processing core.

14. A method as claimed in claim 1, further comprising monitoring said hardware simulator to detect expected changes of state within said hardware component occurring in response to said software stimulus.

15. Apparatus for simulating a system having a software component and a hardware component, said apparatus comprising:

(i) a software simulator for modelling operation of said software component;

(ii) a hardware simulator for modelling operation of said hardware component

(iii) means for linking said hardware simulator and said software simulator to model interaction between said modelled operation of said hardware component and said modelled operation of said software component;

(iv) a test controller for generating, during modelling of said software and hardware components and said interaction, a software stimulus for said software component and a hardware stimulus for said hardware component, said software stimulus and said hardware stimulus are associated so as to permit verification of correct interoperability of said software component and said hardware component, wherein said modelled interaction between said software component and said hardware component proceeds independently of said test cntroller;

(v) said software simulator includes means for modelling a response of said software component to said software stimulus; and

(vi) said hardware simulator includes means for modelling a response of said hardware component to said hardware stimulus, wherein said software stimulus is passed to said software simulator by issuing a remote procedure call from said test controller to said software simulator.

16. A computer program product comprising a computer-readable medium for controlling a computer to simulate a system having a software component and a hardware component, said computer program product comprising:

(i) software simulator logic for modelling operation of said software component;

(ii) hardware simulator logic for modelling operation of said hardware component

(iii) logic linking said hardware simulator logic and said software simulator logic to model interaction between said operation of said hardware component and saiod modelled operation of said software component;

(iv) test controller logic for generating a software stimulus for said software component and a hardware stimulus for said hardware component, said generating occurring during modelling of said software component and said hardware component and said modelled interaction, said software stimulus and said hardware stimulus being associated so as to permit verification of correct interoperability of said software component and said hardware component, wherein said interaction between said software component and said hardware component proceeds independently of said test controller logic;

(v) said software simulator logic includes logic for modelling a response of said software component to said software stimulus; and

(vi) said hardware simulator logic includes logic for modelling a response of said hardware component to said hardware stimulus, wherein said software stimulus is passed to said software simulator logic by issuing a remote procedure call from said test controller logic to said software simulator logic.