Heterogeneous multiprocessor system and OS configuration method thereof

• US 7,366,814 B2
• Filed: 02/21/2006
• Issued: 04/29/2008
• Est. Priority Date: 11/28/2005
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Shimizu, Masaaki, Sukegawa, Naonobu
• Primary Examiner(s): Myers; Paul R.
• Application Number:
  US11/357,088
• Publication Number:
  US 20070124523A1
• Time in Patent Office: 798 Days
• Field of Search: 710260-269
• US Class Current: 710/268
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.

Claims

1. A heterogeneous multiprocessor system including at least first and second processors and one or a plurality of interrupt controllers, said system comprising:

first means which accepts an interrupt in each processor;

second means which inquires said accepted interrupt of an interrupt destination management table to select an interrupt destination processor;

third means which queues said accepted interrupt;

fourth means which generates an interprocessor interrupt to said selected interrupt destination processor;

fifth means which receives said interprocessor interrupt in said interrupt destination processor;

sixth means which performs interrupt process of the interrupt source processor in said interrupt destination processor;

seventh means which generates said interprocessor interrupt to said interrupt source processor in said interrupt destination processor;

eighth means which performs an interrupt end process in said interrupt source processor; and

ninth means which performs interrupt process in its own processor when said interrupt destination processor selected as a result of the inquiry to said interrupt destination management table is its own processor.

2. The heterogeneous multiprocessor system according to claim 1,

wherein said first means includes:

means which accepts an interrupt from an interrupt controller; and

means which accepts an interrupt caused from inside of a processor.

3. The heterogeneous multiprocessor system according to claim 2,

wherein said first means includes codes for each type of the processors which execute an interrupt accepting process.

4. The heterogeneous multiprocessor system according to claim 1,

wherein said second means shares said interrupt destination management table by placing it in a storage device shared in said heterogeneous multiprocessor system or keeps consistency in the interrupt destination management table in a storage device unique to the processor by using interprocessor communication means.

5. The heterogeneous multiprocessor system according to claim 4,

wherein said second means includes:

means which selects an entry of said interrupt destination management table by using a generated processor number and interrupt number; and

means which takes, from said selected entry, information regarding a transfer destination processor, an interrupt level, and whether an end process is required.

6. The heterogeneous multiprocessor system according to claim 5,

wherein said second means includes means which selects a processor in which the interrupt is possible based on mask levels of processors when there are a plurality of processors in which the interrupt is possible in said interrupt destination management table.

7. The heterogeneous multiprocessor system according to claim 5,

wherein said second means includes means which selects a physically close processor in a NUMA configuration or the like when there are a plurality of processors in which the interrupt is possible in said interrupt destination management table.

8. The heterogeneous multiprocessor system according to claim 5,

wherein said second means includes means which selects a processor high in processing capability when there are a plurality of processors in which the interrupt is possible in said interrupt destination management table.

9. The heterogeneous multiprocessor system according to claim 1,

wherein said third means includes:

means which sets, in interrupt information, a flag indicating whether an end interrupt is required in accordance with whether an end process of the selected entry is required; and

means which registers the interrupt information in an interrupt queue.

10. The heterogeneous multiprocessor system according to claim 9,

wherein said third means includes:

means which converts interrupt information of various types of processors to a unified format and registers it in said interrupt queue; and

means which converts interrupt information of various types of interrupt controllers to a unified format and registers it in said interrupt queue.

11. An OS configuration method for a heterogeneous multiprocessor system including at least first and second processors and one or a plurality of interrupt controllers, said method comprising:

a first step of accepting an interrupt in an interrupt source processor;

a second step of generating interrupt information;

a third step of determining an interrupt destination processor of the accepted interrupt by the inquiry to an interrupt destination management table in said interrupt source processor;

a fourth step of registering said interrupt information to an interrupt queue when said interrupt destination processor is its own processor, setting said interrupt information as “

under interrupt process” and

performing an interrupt process in its own processor if the interrupt is possible as a result of the comparison with a current mask level, and returning to a process before the interrupt if the interrupt is not possible as a result of the comparison with the current mask level; and

a fifth step of, if said interrupt destination processor is a processor other than its own processor and an end process is required, setting a flag waiting for an end interrupt in said interrupt information, registering said interrupt information in the interrupt queue, generating an interprocessor interrupt in said interrupt destination processor, and returning to the process before interrupt.

12. The OS configuration method for the heterogeneous multiprocessor system according to claim 11,

wherein said fourth steps includes:

a step of selecting said interrupt information from said interrupt queue to said interrupt destination processor;

a step of comparing an interrupt level included in said interrupt information with an interrupt mask level of an interrupt destination processor context to determine whether an interrupt is possible;

a step of setting an interrupt state of said selected interrupt information as “

under interrupt process”

;

a step of storing a processor context before interrupt in an entry of a processor context queue in said interrupt destination processor;

a step of generating a new processor context entry and registering it in said processor context queue in said interrupt destination processor; and

a step of taking an interrupt vector from a vector table of said interrupt destination processor to execute it.

13. The OS configuration method for the heterogeneous multiprocessor system according to claim 12,

wherein said fourth step includes:

a step of informing a hypervisor of an end of interrupt process when the interrupt process in said interrupt destination processor ends;

a step of selecting interrupt information corresponding to the interrupt being processed from said interrupt queue;

a step of setting said selected interrupt information as “

end of interrupt process”

;

a step of generating an interprocessor interrupt to a transfer source processor when the interrupt transfer source is a processor other than its own processor and an end interrupt has to be generated;

a step of performing an interrupt end process of the processor or the interrupt controller and deleting the interrupt information from said interrupt queue when said interrupt transfer source is its own processor; and

a step of deleting a current context from said processor context queue and executing a process with using a context before interrupt as a current context.

14. The OS configuration method for the heterogeneous multiprocessor system according to claim 13,

wherein said fourth step includes:

a step of selecting interrupt information indicating “

end of interrupt process”

from said interrupt queue;

a step of performing the interrupt end process of said processor or interrupt controller and deleting the interrupt information from said interrupt queue; and

a step of deleting the current context from said processor context queue and executing the process with using the context before interrupt as the current context.