Method and test device for detecting addressing errors in control units
First Claim
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1. A method of detecting addressing errors in a control unit, the method comprising the acts of:
- writing preset test data of a preset model in a successive manner with respect to time into all addressable memory cells of the control unit while the control unit is deactivated by a user with respect to a normal operation;
subsequently reading out and comparing data from the addressable memory cells with the test data;
generating an error message, if applicable, as a function of the comparing act; and
wherein for all addressable memory cells, different test data are written in accordance with the preset model, and wherein the error message is stored if applicable and emitted only when the control unit is reactivated.
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Abstract
The invention relates to a method for detecting addressing errors in control devices of motor vehicles, whereby test data are input into all addressable memory cells by means of a present model, then read out and compared with the test data.
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Citations
13 Claims
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1. A method of detecting addressing errors in a control unit, the method comprising the acts of:
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writing preset test data of a preset model in a successive manner with respect to time into all addressable memory cells of the control unit while the control unit is deactivated by a user with respect to a normal operation; subsequently reading out and comparing data from the addressable memory cells with the test data; generating an error message, if applicable, as a function of the comparing act; and wherein for all addressable memory cells, different test data are written in accordance with the preset model, and wherein the error message is stored if applicable and emitted only when the control unit is reactivated. - View Dependent Claims (2, 3, 4)
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5. A test device for detecting addressing errors in a control unit having an addressable memory with several individually addressable memory cells, comprising:
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a test generator which writes a preset model of test data into the individually addressable memory cells; a comparator which reads out the test data previously written into the individually addressable memory cells and compares the read out test data with the preset model of test data; a control operably coupled to activate the test data generator when the control unit is deactivated with respect to its normal operation; an error memory coupled to the comparator, in which faulty comparison results are stored and emitted only when the control unit is reactivated.
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6. A method for detecting addressing errors in control units, the method comprising the acts of:
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inputting test data into all addressable memory cells of the control unit via a preset model when the control unit is switched-off by the user; subsequently reading out the input test data; and comparing the subsequently read out input test data with the test data input via the preset model in order to detect any errors. - View Dependent Claims (7, 8, 9, 10)
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11. A test device for detecting addressing errors in a control unit having an addressable memory with several individually addressable memory cells, comprising:
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a test data generator operably coupled to write into the individually addressable memory cells test data in accordance with a preset model; a comparator operably configured to read out the previously written in test data from the individually addressable memory cells and compare the read out test data with the written in test data in accordance with the preset model in order to detect addressing errors; and a control operably configured to activate the test data generator when the control unit is switched-off. - View Dependent Claims (12, 13)
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Specification