Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program
First Claim
1. A method for simulating a power voltage distribution, comprising the steps of:
- dividing a layout area of a semiconductor integrated circuit into a plurality of division units and acquiring power occupancy ratio information that expresses a power wiring density in the division units;
acquiring power I/O position information, which expresses at least one position to which power is fed in the layout area;
obtaining a resistance value of a model resistor, which expresses the resistance value of power wiring between the division units adjacent to each other, in response to a predetermined sheet resistance value of the power wiring and the power occupancy ratio information; and
defining a division unit at least a part of which overlaps a predetermined area disposed by at least one so that the predetermined area occupies at least a part of the layout area as a division unit belonging to the predetermined area, and uniformly allotting a consumption current consumed in the predetermined area to the division units belonging to the predetermined area.
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Abstract
The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven distribution of a floor plan taken into account. In Step S1, design information (Core size CS, core ring width CW, block shape BS, macro shape MS, block current BI, macro current MI, etc.) is inputted into a simulator. In Step S2, information regarding a floor plan (Block position BP, macro position MP, power I/O position IOP) is inputted into the simulator by a designer. In Step S3, the power unit management table is initialized, and resistance modeling and current source modeling are also carried out. In Step S5 (FIG. 1), the static IR drop is calculated based on the power unit management table CT obtained in Step S4.
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Citations
10 Claims
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1. A method for simulating a power voltage distribution, comprising the steps of:
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dividing a layout area of a semiconductor integrated circuit into a plurality of division units and acquiring power occupancy ratio information that expresses a power wiring density in the division units; acquiring power I/O position information, which expresses at least one position to which power is fed in the layout area; obtaining a resistance value of a model resistor, which expresses the resistance value of power wiring between the division units adjacent to each other, in response to a predetermined sheet resistance value of the power wiring and the power occupancy ratio information; and defining a division unit at least a part of which overlaps a predetermined area disposed by at least one so that the predetermined area occupies at least a part of the layout area as a division unit belonging to the predetermined area, and uniformly allotting a consumption current consumed in the predetermined area to the division units belonging to the predetermined area. - View Dependent Claims (2, 5, 6, 7, 8, 9)
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3. A method for simulating a power voltage distribution, which is provided with a plurality of types of circuit aggregates composed of a combination of a plurality of circuits, having the circuit aggregates disposed in a core area, in which circuits pertaining to main actions are disposed, in the layout area, comprising the steps of:
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acquiring information of circuit aggregate positions expressing positions of the circuit aggregates disposed in the core area; acquiring information of circuit aggregate shapes expressing the shapes of the circuit aggregates; acquiring information of circuit aggregate current amounts expressing a current consumed by the corresponding circuit aggregate in compliance with the type of the circuit aggregate; acquiring information of chip total current being a current consumed by the entirety of the semiconductor integrated circuit; calculating an area occupied by circuit aggregates, at which the respective circuit aggregates exist on the core area, based on the information of circuit aggregate positions and the information of circuit aggregate shapes, and extracting the number of the division units belonging to the area occupied by the circuit aggregates for each of the circuit aggregates; and obtaining a resistance value of the model resistor based on the power occupancy ratio information and the sheet resistance value, which are determined in compliance with a type of the circuit aggregate to which the division units belong; wherein the consumption current value in the division units belonging to the area occupied by the circuit aggregates is obtained by dividing the current value of the information of the circuit aggregate current amount by the number of the division units belonging to the area occupied by the circuit aggregates; and the consumption current amount in the division units not belonging to the area occupied by the circuit aggregates is obtained by dividing the remaining value, which is obtained by subtracting the totaled value of the information of the circuit aggregate current amounts for all the circuit aggregates from the chip total current information, by the number of the division units not belonging to any area occupied by the circuit aggregates. - View Dependent Claims (4)
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10. A program embodied in a computer-readable medium for simulating a power voltage distribution, comprising the steps of:
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dividing a layout area of a semiconductor integrated circuit into a plurality of division units and acquiring power occupancy ratio information that expresses a power wiring density in the division units; acquiring power I/O position information, which expresses at least one position to which power is fed in the layout area; obtaining a resistance value of a model resistor, which expresses the resistance value of power wiring between the division units adjacent to each other, in response to a predetermined sheet resistance value of the power wiring and the power occupancy ratio information; defining a division unit at least a part of which overlaps a predetermined area disposed by at least one so that the predetermined area occupies at least a part of the layout area as a division unit belonging to the predetermined area, and uniformly allotting a consumption current consumed in the predetermined area to the division units belonging to the predetermined area.
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Specification