Trench power MOSFET with reduced gate resistance

• US 7,368,353 B2
• Filed: 11/04/2004
• Issued: 05/06/2008
• Est. Priority Date: 11/04/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Burke, Hugo, Kent, Dave, Montgomery, Robert, Cao, Jianjun, Spring, Kyle, Harvey, Paul
• Primary Examiner(s): Fourson; George R.
• Assistant Examiner(s): Maldonado; Julio J
• Application Number:
  US10/981,114
• Publication Number:
  US 20050112823A1
• Time in Patent Office: 1,279 Days
• Field of Search: 438/270, 438/272, 438/424, 438/430, 438/221, 438/212, 438/296, 438/589, 257/E29.257, 257/E21.419, 257/E21.546, 257/E21.629, 257/E21.622
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof.

Claims

1. A method for manufacturing a power semiconductor device comprising:

forming a mask layer over a first surface of a semiconductor body;

patterning said mask layer with a plurality of openings each opening extending to and exposing said first surface of said semiconductor body at the bottom thereof;

etching a termination trench in said semiconductor body prior to patterning said mask layer, said termination trench including a side wall and bottom, extending to a depth below a first depth and defining an active area that includes said trenches;

defining trenches in said semiconductor body by etching said semiconductor body through said openings, each trench including sidewalls and a bottom;

forming an insulation layer on said sidewalls of said trenches;

forming a gate electrode in each of said trenches, each gate electrode including a free end extending above said first surface into a respective opening in said mask layer to a height substantially co-planar with a top surface of said mask layer;

siliciding each of said gate electrodes at its free end;

removing said mask layer, whereby each gate electrode becomes proud and extends above said first surface of said semiconductor body;

implanting continuous source implant regions of first conductivity in said semiconductor body between said trenches;

forming spaced insulation interlayers over said free ends of said gate electrodes;

etching through said source implant regions;

implanting regions of second conductivity into said semiconductor body through spaces between said spaced interlayers to form implant regions of said second conductivity; and

applying a diffusion drive to form source regions and high conductivity contact regions of said second conductivity.

2. A method according to claim 1, wherein said mask layer is comprised of silicon nitride.

3. A method according to claim 1, wherein said gate electrodes are formed by first forming gate electrode material inside said trenches and over said mask layer and then removing gate electrode material that overlies said mask layer.

4. A method according to claim 1, further comprising forming a channel region of a second conductivity in said semiconductor body, said channel region extending to a first depth;

and wherein said source regions are formed in said channel region and terminate at a depth shallower than said first depth.

5. A method according to claim 1, wherein said source regions are formed in said channel region and extend to a depth that is shallower than said first depth.

6. A method for manufacturing a power semiconductor device comprising:

forming a mask layer over a first surface of a semiconductor body;

patterning said mask layer with a plurality of openings each opening extending to and exposing said first surface of said semiconductor body at the bottom thereof;

defining trenches in said semiconductor body by etching said semiconductor body through said openings, each trench including sidewalls and a bottom;

forming an insulation layer on said sidewalls of said trenches;

forming a gate electrode in each of said trenches, each gate electrode including a free end extending above said first surface into a respective opening in said mask layer to a height substantially co-planar with a top surface of said mask layer;

siliciding each of said gate electrodes at its free end;

removing said mask layer, whereby each gate electrode becomes proud and extends above said first surface of said semiconductor body;

implanting continuous source implant regions of first conductivity in said semiconductor body between said trenches;

forming spaced insulation interlayers over said free ends of said gate electrodes;

etching through said source implant regions;

implanting regions of second conductivity into said semiconductor body through spaces between said spaced interlayers to form implant regions of said second conductivity; and

applying a diffusion drive to form source regions and high conductivity contact regions of said second conductivity;

forming a channel region of a second conductivity in said semiconductor body to a first depth within said semiconductor body, said trenches extending to a depth below said first depth; and

etching a termination trench in said semiconductor body prior to patterning said mask layer, said termination trench including a side wall and bottom, extending to a depth below said first depth and defining an active area that includes said trenches;

forming a field insulation body over said sidewall and said bottom of said termination trench;

forming an electrically conductive layer over said field insulation and said mask layer; and

etching said electrically conductive layer that overlies said mask layer to define a termination electrode in said termination trench.

7. A method according to claim 6, further comprising siliciding said termination electrode.