Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body

• US 7,368,358 B2
• Filed: 02/02/2006
• Issued: 05/06/2008
• Est. Priority Date: 10/31/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Xiangdong, Ouyang, Qiqing C.
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US11/345,955
• Publication Number:
  US 20060128105A1
• Time in Patent Office: 824 Days
• Field of Search: 438/481
• US Class Current: 438/299
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors

Abstract

A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.

Claims

1. A method for producing a field effect device, comprising:

providing a body for said device, wherein said body is a monocrystalline Si layer on an insulator;

in source/drain regions of said body, recessing said body all the way to said insulator;

fabricating a source and a drain for said device, wherein said source and said drain are grown epitaxially in a lateral direction in said source/drain regions by using a lateral seeding from said body, wherein said source and said drain are selected to consist essentially of SiGe, wherein said source and said drain each form a heterojunction with said body.

2. The method of claim 1, further comprising:

providing a channel between said source and said drain, wherein said channel is selected to consists essentially of SiGe.

3. The method of claim 2, wherein said SiGe channel is selected to be between about 5 nm and 15 nm thick.

4. The method of claim 1, further comprising:

providing a channel between said source and said drain, wherein said channel is selected to consists essentially of said Si.

5. The method of claim 1, further comprising:

forming a metallurgical junction between said body and each of said source and said drain by providing said body with one conductivity type and providing said source and said drain with an opposing conductivity type, wherein said heterojunction and said metallurgical junction coincide with a tolerance of less than about 10 nm.

6. The method of claim 5, wherein said body conductivity is selected one of n-type or p-type.

7. The method of claim 1, wherein said SiGe is selected to be in one of an undoped state or a p-doped state.

8. The method of claim 1, wherein said SiGe is selected to have a Ge concentration of between about 15% and 50%.

9. The method of claim 1, further comprising:

capping said SiGe with an epitaxial layer of Si having a thickness of between about 2 nm and 30 nm.

10. The method of claim 1, wherein said device has a top surface plane and said source and said drain are fabricated to raise above said top surface plane.