Ground shields for semiconductors

• US 7,368,668 B2
• Filed: 02/03/2006
• Issued: 05/06/2008
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Lamey, Daniel J., Ren, Xiaowei, Pryor, Robert A.
• Primary Examiner(s): Ngo; Hung V.
• Application Number:
  US11/347,461
• Publication Number:
  US 20070181339A1
• Time in Patent Office: 823 Days
• Field of Search: 257/239, 257/659, 257/660, 174/382, 174/377
• US Class Current: 174/382
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/30111 matching
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device, such as a RF LDMOS, having a ground shield that has a pair of stacked metal layers. The first metal layer extends along the length of the semiconductor device and is formed on the upper surface of the semiconductor device body. The first layer has a series of regularly spaced apart lateral first slots. The second metal layer, coextensive with and located above the first metal layer, has a series of regularly spaced apart lateral second slots. The second slots overlie the spaces between the first slots, and the continuous portions of the second metal layer overlie the first slots. The slots are substantially parallel to wires extending over the ground shield. The ground shield is not limited to only two metal layers. The ground shield has a repeating unit design that facilitates automated design.

Claims

1. A ground shield for a semiconductor device of the type that includes a set of conductive wires, comprising:

a first metal layer on a semiconductor body, the first layer comprising a series of regularly spaced apart lateral first slots therein; and

a second metal layer above the first metal layer, the second layer comprising a series of regularly spaced apart lateral second slots therein, the second slots overlying spaces between the first slots, and the second metal layer overlying the first slots;

wherein each of the first and second metal layers are electrically contiguous and are positioned over the set of conductive wires such that the first and second metal layers form the ground shield with respect to the conductive wires.

2. The ground shield of claim 1, wherein the second slots comprise therein islands of an interlevel dielectric ILD1, the islands laid on the first metal layer.

3. The ground shield of claim 1, wherein the first slots comprise therein islands of an interlevel dielectric ILD0, the ILD0 islands having a width Y1.

4. The ground shield of claim 3, wherein an ILD0 island is overlaid by an island of ILD1 having a width of Y2, where Y2 is greater than or equal to Y1.

5. The ground shield of claim 1, wherein a contact area of the first metal layer on a semiconductor body is less than about sixty percent based on the ground shield area.

6. The ground shield of claim 1, wherein a via area of the second metal layer on the first metal layer is less than about forty percent based on the ground shield area.

7. The ground shield of claim 1, wherein the area of the ground shield is greater than about five square millimeters.

8. A semiconductor device comprising:

a semiconductor body;

an inboard wire pad located on the semiconductor body and extending along a length of the device;

an outboard wire pad located on the semiconductor body, extending along a length of the device, the outboard pad spaced further from a longitudinal axis of the chip than the inboard pad; and

a ground shield located between the inboard and outboard pad, the ground shield extending along a length of the device, the ground shield comprising;

a first metal layer on the semiconductor body, the first layer comprising a series of regularly spaced apart lateral first slots therein; and

a second metal layer above the first metal layer, the second layer comprising a series of regularly spaced apart lateral second slots therein, the second slots overlying spaces between the first slots, and the second metal layer overlying the first slots.

9. The device of claim 8, further comprising a wire extending over the ground shield, from the inboard pad to the outboard wire pad, substantially parallel to slots in the first and second metal layers.

10. The device of claim 9, wherein slotted patterning of the first and second metal layers form a repeating unit of the ground shield.

11. The device of claim 8, wherein the second slots comprise therein interlevel dielectric ILD1, the ILD1 laid on the first metal layer.

12. The device of claim 8, wherein first slots comprise therein islands of interlevel dielectric ILD0, each island of ILD0 having a width Y1.

13. The device of claim 12, wherein ILD0 islands are overlaid with islands of ILD1, each ILD1 island having a width of Y2, where Y2 is greater than or equal to Y1.

14. The device of claim 8, wherein a contact area of the first metal layer on a semiconductor body is less than is less than about sixty percent based on the ground shield area.

15. The device of claim 8, wherein a via area of the second metal layer on the first metal layer is less than about forty percent based on the ground shield area.

16. The device of claim 8, wherein the area of the ground shield is greater than about five square millimeters.

17. The device of claim 8, wherein the device comprises an RF LDMOS chip.

18. The device of claim 17, wherein the device further comprises a highly doped implant layer under the ground shield and a back-side ground.