Semiconductor device

• US 7,368,783 B2
• Filed: 09/21/2005
• Issued: 05/06/2008
• Est. Priority Date: 01/23/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mizukami, Makoto, Shinohe, Takashi
• Primary Examiner(s): Warren; Matthew E.
• Application Number:
  US11/230,492
• Publication Number:
  US 20060011973A1
• Time in Patent Office: 958 Days
• Field of Search: 257327-331, 257/334, 257/E29.257, 257/E29.26, 257/E29.262
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface and a second major surface;

a lightly-doped semiconductor layer of a first conductivity type, formed on the first major surface of the semiconductor substrate;

an active region formed on a top of an island-shaped region on a surface of the lightly-doped semiconductor layer, the active region including a first semiconductor region of a second conductivity type formed on the lightly-doped semiconductor layer, and a second semiconductor region of the first conductivity type formed on the first semiconductor region;

a first electrode surrounding the active region and extending toward the lightly-doped semiconductor layer to a deeper position than the active region;

a first insulating film formed at least between a side surface of the active region and the first electrode;

a buried field relaxation layer formed in the lightly-doped semiconductor layer adjacent to a bottom surface of the first electrode, the buried field relaxation layer including a first field relaxation layer of the second conductivity type and second field relaxation layers of the first conductivity type formed at two ends of the first field relaxation layer;

a second electrode formed on the second semiconductor region on the first major surface; and

a third electrode formed on the second major surface.

2. The device according to claim 1, wherein the first insulating film is further formed on a bottom surface of the first electrode, and is disposed between the first electrode and at least one of the first field relaxation layer and the second field relaxation layers.

3. The device according to claim 1, further comprising a first impurity layer of the second conductivity type formed between a bottom surface of the first electrode and the lightly-doped semiconductor layer.

4. The device according to claim 1, further comprising third semiconductor regions of the second conductivity type at two ends of the second semiconductor region and in contact with the second electrode.

5. The device according to claim 1, further comprising a fourth semiconductor region which connects the first field relaxation layer to the second electrode.

6. The device according to claim 1, wherein an impurity concentration in the second field relaxation layer is higher than an impurity concentration in the lightly-doped semiconductor layer.

7. The device according to claim 1, wherein the semiconductor substrate is formed as a first conductivity type.

8. The device according to claim 1, wherein the semiconductor substrate is formed as a second conductivity type.

9. A semiconductor device comprising:

a semiconductor substrate having a first major surface and a second major surface;

a first lightly-doped semiconductor layer of a first conductivity type formed on the first major surface of the semiconductor substrate;

a second lightly-doped semiconductor layer of the first conductivity type formed on the first lightly-doped semiconductor layer;

a third lightly-doped semiconductor layer of the first conductivity type formed on the second lightly-doped semiconductor layer;

an active region formed on a top of an island-shaped region on a surface of the third lightly-doped semiconductor layer, the active region including a first semiconductor region of a second conductivity type formed on the third lightly-doped semiconductor layer, and a second semiconductor region of the first conductivity type formed on the first semiconductor region;

a first electrode surrounding the active region and buried to a deeper position than the first semiconductor region so as to extend through the third lightly-doped semiconductor layer;

a first insulating film formed at least between a side surface of the active region and the first electrode;

a buried field relaxation layer formed in the second lightly-doped semiconductor layer, the buried field relaxation layer including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer;

a second electrode formed on the second semiconductor region of the active region; and

a third electrode formed on the second major surface.

10. The device according to claim 9, wherein the first insulating film is further formed on a bottom surface of the first electrode, and is disposed between the first electrode and at least one of the first field relaxation layer and the second field relaxation layers.

11. The device according to claim 9, further comprising a first impurity layer of the second conductivity type formed between a bottom surface of the first electrode and the second lightly-doped semiconductor layer.

12. The device according to claim 9, further comprising third semiconductor regions of the second conductivity type at two ends of the second semiconductor region and in contact with the second electrode.

13. The device according to claim 9, further comprising a fourth semiconductor region which connects the first field relaxation layer to the second electrode.

14. The device according to claim 9, wherein an impurity concentration in the second field relaxation layer is higher than an impurity concentration in the second lightly-doped semiconductor layer.

15. The device according to claim 9, wherein the semiconductor substrate is formed as a first conductivity type.

16. The device according to claim 9, wherein the semiconductor substrate is formed as a second conductivity type.

17. A semiconductor device, comprising:

a semiconductor substrate;

a first semiconductor layer of a second conductivity type formed on the semiconductor substrate;

a second semiconductor layer of a first conductivity type formed on the first semiconductor layer;

a plurality of highly-doped first semiconductor regions of the first conductivity type having a stripe shape and buried in the second semiconductor layer in line;

a highly-doped second semiconductor region of the first conductivity type buried in the second semiconductor layer apart from and in parallel with the first semiconductor regions;

a gate electrode of a rectangle shape buried in the second semiconductor layer, a first sidewall and a second sidewall of which are opposed to each other and disposed between adjacent ones of the plurality of first semiconductor regions, and a third sidewall between the first sidewall and the second sidewall of which is between the first semiconductor region and the second semiconductor region;

a third semiconductor region of the second conductivity disposed adjacent to and parallel with the third sidewall between the first sidewall and the second sidewall of the gate electrode and buried in the second semiconductor layer; and

fourth semiconductor regions of a first conductivity type disposed at both ends of the third semiconductor region.

18. The device according to claim 17, further comprising a gate insulating film between the first sidewall of the gate electrode and the second semiconductor layer and between the second sidewall of the gate electrode and the second semiconductor layer.

19. The device according to claim 17, further comprising a gate insulating film buried and formed along the third sidewall of the gate electrode, and disposed between the gate electrode and at least one of the third semiconductor region and the fourth semiconductor regions.

20. The device according to claim 17, further comprising a fifth semiconductor region which connects the third semiconductor region with the first semiconductor region.