Multi-gate carbon nano-tube transistors

• US 7,368,791 B2
• Filed: 08/29/2005
• Issued: 05/06/2008
• Est. Priority Date: 08/23/2002
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhang, Yuegang, Doyle, Brian S., Bourianoff, George I.
• Primary Examiner(s): Doan; Theresa T
• Application Number:
  US11/215,559
• Publication Number:
  US 20070281409A1
• Time in Patent Office: 981 Days
• Field of Search: 977/742, 977/842, 438/82, 438/99, 257/401, 257/419
• US Class Current: 257/401
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/482 the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

According to one aspect of the invention, a semiconducting transistor is described. The channel portion of the transistor includes carbon nanotubes formed on top of an insulating layer which covers a local bottom gate. Source and drain conductors are located at ends of the carbon nanotubes. A gate dielectric surrounds a portion of the carbon nanotubes with a substantially uniform thickness. A local top gate is located between the source and drain conductors over the carbon nanotubes. Lower portions of the local top gate are positioned between the carbon nanotubes as the local top gate forms pi-gates or “wraparound” gates around each carbon nanotube.

Claims

1. A method for constructing a semiconductor transistor, comprising:

forming a local bottom gate electrode on a substrate;

forming a first insulating layer on the bottom gate electrode;

depositing an iron catalyst on the first insulating layer;

growing a semiconducting carbon nanotube from the iron catalyst such that the carbon nanotube is chemically bonded to the iron catalyst and is located on the first insulating layer over the local bottom gate electrode, the semiconducting carbon nanotube having an elongate axis, source and drain ends, and a channel portion between the source and drain ends;

forming source and drain conductors over the respective source and drain ends of the semiconducting carbon nanotube;

forming a second insulating layer on the source and drain conductors and the channel portion of the semiconducting carbon nanotube; and

forming a local top gate electrode over the channel portion of the semiconducting carbon nanotube, the local top gate electrode, in at least one cross-section transverse to the elongate axis of the semiconducting carbon nanotube, being electronically disconnected from the local bottom gate electrode, the local bottom gate electrode and the local top gate electrode being located such that when a voltage is applied to the local top and bottom gate electrodes, the source and drain conductors are electrically coupled through the semiconducting carbon nanotube.

2. The method of claim 1, wherein the first and second insulating layers comprise zirconium oxide.

3. The method of claim 1, wherein an electric field is applied to the semiconducting carbon nanotube as it is being grown.

4. A method for constructing a semiconductor transistor, comprising:

forming a local bottom gate electrode on a substrate;

forming an insulating layer on the bottom gate electrode;

positioning a semiconducting carbon nanotube on the insulating layer over the local bottom gate electrode, the semiconducting carbon nanotube having an elongate axis, source and drain ends, and a channel portion between the source and drain ends;

forming source and drain conductors over the respective source and drain ends of the semiconducting carbon nanotube;

forming a gate dielectric on the source and drain conductors and the channel portion of the semiconducting carbon nanotube; and

forming a local top gate electrode over the channel portion of the semiconducting carbon nanotube, the local top gate electrode, in at least one cross-section transverse to the elongate axis of the semiconducting carbon nanotube, being electronically disconnected from the local bottom gate electrode, the local bottom gate electrode and the local top gate electrode being located such that when a voltage is applied to the local top and bottom gate electrodes, the source and drain conductors electrically coupled through the semiconducting carbon nanotube,

wherein the semiconducting carbon nanotube has a curved outer surface, the gate dielectric being adjacent to the curved outer surface of the semiconducting nanotube, only a portion of the gate dielectric having a curved outer gate dielectric surface.

5. The method of claim 4, wherein the portion of the gate dielectric with the curved outer gate dielectric surface has a substantially uniform thickness.