Tamper response system for integrated circuits

• US 7,368,935 B2
• Filed: 10/18/2005
• Issued: 05/06/2008
• Est. Priority Date: 10/18/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Bernier, Brian R., Waltuch, Jason
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US11/253,006
• Publication Number:
  US 20070086257A1
• Time in Patent Office: 931 Days
• Field of Search: 326 8- 9, 326/38
• US Class Current: 326/8
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit is adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.

Claims

1. A tamper response system comprising:

at least one sensor adapted to sense tamper activity; and

a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal;

wherein the tamper circuit is disabled after the at least one FPGA has been cleared.

2. The tamper response system of claim 1, wherein the tamper circuit is located remote to the at least one FPGA in a volatile memory, the tamper circuit further adapted to shut power off to it-self after the at least one FPGA has been cleared.

3. The tamper response system of claim 1, wherein the tamper circuit resides on one of the at least one FPGA, the tamper circuit adapted to remove a pointer to the tamper circuit after the one FPGA has been cleared.

4. The tamper response system of claim 1, wherein the tamper circuit clears the at least one FPGA by toggling an interface clearance pin on the at least one FPGA that is adapted to clear the at least one FPGA when toggled.

5. The tamper response system of claim 1, wherein the at least one sensor is at least one of a fiber optic sensor, an infra-red sensor, a vibration sensor, a thermal sensor, an acoustic sensor, noise sensor, a light sensor, a pressure sensor, a volumetric sensor, a stress sensor, a LOS sensor, a biometric sensor, a humidity sensor, a surge sensor, a voltage sensor, a radio frequency interface (RFI) sensor and a electromagnetic interface (EMI) sensor.

6. The tamper response system of claim 1, wherein the tamper circuit is further adapted to disconnect a power source to the at least one FPGA upon receipt of the tamper signal.

7. The tamper response system of claim 1, wherein in the tamper circuit is further adapted to erase information in at least one memory upon receipt of the tamper signal.

8. The tamper system of claim 7, wherein the tamper circuit is further adapted to erase information in the at least one memory by a predefined sequence, wherein information needing the highest level of protection is erased first.

9. A tamper system comprising:

at least one sensor adapted to sense tamper activity; and

a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to erase information in at least one memory upon receipt of a tamper signal;

wherein the tamper circuit is disabled after the information from the at least one memory has been cleared.

10. The tamper system of claim 9, wherein the tamper circuit is further adapted to erase information in the at least one memory by a predefined sequence, wherein information needing the highest level of protection is erased first.

11. The tamper response system of claim 9, wherein the at least one sensor is at least one of a fiber optic sensor, an infra-red sensor, a vibration sensor, a thermal sensor, an acoustic sensor, a noise sensor, a light sensor, a pressure sensor, a volumetric sensor, a stress sensor, a LOS sensor, a biometric sensor, a humidity sensor, a surge sensor, a voltage sensor, a radio frequency interface (RFI) sensor and an electromagnetic interface (EMI) sensor.

12. The tamper system of claim 9, wherein the tamper circuit is further adapted to clear at least one field programmable gate may (FPGA) upon receipt of a tamper signal.

13. The tamper response system of claim 12, wherein the tamper circuit is located remote in a volatile memory, the tamper circuit further adapted to shut power off to it-self after the at least one FPGA has been cleared.

14. The tamper response system of claim 12, wherein the tamper circuit resides on the at least one FPGA, the tamper circuit adapted to remove a pointer to the tamper circuit after the at least one FPGA has been cleared.

15. A tamper circuit comprising:

a sensor input adapted to receive tamper signals from one or more sensors;

an FPGA control output adapted to send a FPGA clearance signal to an FPGA to clear the FPGA;

a memory erase output adapted to erase a memory in communication with the memory erase output; and

a control circuit adapted to process tamper signals received at the sensor input, the control circuit further adapted to send the FPGA clearance signal to the FPGA control output and to control the memory erase output based on the processed tamper signals;

wherein the tamper circuit is disabled after the FPGA has been cleared and the memory has been erased.

16. The tamper circuit of claim 15, wherein the control circuit is further adapted to erase information in the memory based on a defined priority sequence.

17. The tamper circuit of claim 15, wherein the tamper circuit is volatile and the control circuit is further adapted to disconnect power to itself after the memory and FPGA have been cleared.

18. The tamper circuit of claim 15, wherein the control circuit resides on the FPGA and the control circuit is further adapted to disconnect a pointer to the tamper circuit upon completion of the clearing of the FPGA and the erasing information in the memory.

19. The tamper circuit of claim 15, wherein the control circuit is further adapted to disconnect power to the FPGA to disable a key of the FPGA.

20. A method of protecting data in a FPGA using a tamper sensor coupled to a tamper circuit to detect tamper activity, the method comprising:

sensing tamper activity;

in response to the sensing of tamper activity, overwriting the FPGA; and

disabling the tamper circuit after the FPGA has been overwritten.

21. The method of claim 20, wherein overwriting the FPGA further comprises:

toggling an interface clearance pin on the FPGA with the tamper circuit.

22. The method of claim 21, further comprising:

in response to the sensing of tamper activity, erasing at least one memory.

23. The method of claim 22, wherein erasing the at least one memory further comprises:

erasing information in the at least one memory in a predefined sequence such that information that is the most sensitive is erased first.

24. The method of claim 21, wherein the tamper circuit is located on the FPGA and the method further comprises:

removing a pointer to the tamper circuit in the FPGA after the FPGA has been cleared.

25. The method of claim 21, wherein the tamper circuit is volatile, the method further comprising:

disconnecting power to the tamper circuit after the FPGA has been cleared.

26. A machine readable medium having instructions stored thereon for protecting digital information, the method comprising:

processing tamper signals from one or more tamper sensors on a tamper circuit;

manipulating an interface clearance input on an FPGA to clear the FPGA of information based on the processed tamper signals;

erasing at least one memory based on the processed tamper signals; and

disabling the tamper circuit after the FPGA has been cleared and the at least one memory has been erased.

27. The machine readable instructions of claim 26, further comprising:

erasing information in the a least one memory in a predefine sequence such that information that is the most valuable is erased first.

28. The machine readable instructions of claim 26, further comprising:

removing a pointer to the tamper circuit in the FPGA when information in the FPGA and the at least one memory is cleared.

29. The machine readable instructions of claim 26, further comprising:

disconnecting power to the tamper circuit when information in the FPGA and the at least one memory is cleared.

30. A digital data tamper system, the system comprising:

a means to detect tamper activity;

a means to clear at least one FPGA upon detection of tamper activity;

a means to erase at least one memory upon detection of the tamper activity; and

a means to prevent the detection of the digital tamper system after the at least one FPGA has been cleared and the at least one memory has been erased.