Tamper response system for integrated circuits
First Claim
Patent Images
1. A tamper response system comprising:
- at least one sensor adapted to sense tamper activity; and
a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal;
wherein the tamper circuit is disabled after the at least one FPGA has been cleared.
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Abstract
A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit is adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.
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Citations
30 Claims
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1. A tamper response system comprising:
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at least one sensor adapted to sense tamper activity; and a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal; wherein the tamper circuit is disabled after the at least one FPGA has been cleared. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A tamper system comprising:
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at least one sensor adapted to sense tamper activity; and a tamper circuit coupled to receive tamper signals from the at least one sensor, the tamper circuit adapted to erase information in at least one memory upon receipt of a tamper signal; wherein the tamper circuit is disabled after the information from the at least one memory has been cleared. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A tamper circuit comprising:
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a sensor input adapted to receive tamper signals from one or more sensors; an FPGA control output adapted to send a FPGA clearance signal to an FPGA to clear the FPGA; a memory erase output adapted to erase a memory in communication with the memory erase output; and a control circuit adapted to process tamper signals received at the sensor input, the control circuit further adapted to send the FPGA clearance signal to the FPGA control output and to control the memory erase output based on the processed tamper signals; wherein the tamper circuit is disabled after the FPGA has been cleared and the memory has been erased. - View Dependent Claims (16, 17, 18, 19)
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20. A method of protecting data in a FPGA using a tamper sensor coupled to a tamper circuit to detect tamper activity, the method comprising:
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sensing tamper activity; in response to the sensing of tamper activity, overwriting the FPGA; and disabling the tamper circuit after the FPGA has been overwritten. - View Dependent Claims (21, 22, 23, 24, 25)
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26. A machine readable medium having instructions stored thereon for protecting digital information, the method comprising:
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processing tamper signals from one or more tamper sensors on a tamper circuit; manipulating an interface clearance input on an FPGA to clear the FPGA of information based on the processed tamper signals; erasing at least one memory based on the processed tamper signals; and disabling the tamper circuit after the FPGA has been cleared and the at least one memory has been erased. - View Dependent Claims (27, 28, 29)
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30. A digital data tamper system, the system comprising:
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a means to detect tamper activity; a means to clear at least one FPGA upon detection of tamper activity; a means to erase at least one memory upon detection of the tamper activity; and a means to prevent the detection of the digital tamper system after the at least one FPGA has been cleared and the at least one memory has been erased.
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Specification