Output buffer circuit

• US 7,368,952 B2
• Filed: 04/22/2005
• Issued: 05/06/2008
• Est. Priority Date: 04/22/2004
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ojiro, Tsukasa
• Primary Examiner(s): Cho, James
• Assistant Examiner(s): Crawford, Jason
• Application Number:
  US11/111,732
• Publication Number:
  US 20050237085A1
• Time in Patent Office: 1,110 Days
• Field of Search: 326 82- 83, 326 86- 87, 327108-109
• US Class Current: 326/87
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

An output buffer circuit includes a first output buffer section and a second output buffer section. The first output buffer section includes complementary semiconductors. The second output buffer section includes complementary semiconductors and is connected in parallel with the first output buffer section. The second output buffer section starts to output an second output signal after an output voltage of the output buffer circuit reaches a reference voltage indicative of one of an on-state and an off-state by a first output signal of the first output buffer section.

Claims

1. An output buffer circuit comprising:

an input terminal for receiving a input signal;

a first output buffer section including complementary semiconductors and outputting a first output signal corresponding to said input signal;

a second output buffer section including complementary semiconductors and connected in parallel with said first output buffer section,

wherein said second output buffer section starts to output a second output signal corresponding to said input signal after said first output signal corresponding to said input signal reaches a reference voltage Von to decide whether an output voltage of said output buffer circuit is on-state or off-state;

a first predriver section receiving said input signal and applying a first gate voltage to a control terminal of said first output buffer section; and

a second predriver section receiving said input signal and applying a second gate voltage to a control terminal of said second output buffer section,

wherein said first gate voltage crosses through a voltage level of a threshold voltage of said first output buffer section in response to a voltage change of said input signal before said output voltage of said output buffer circuit reaches said reference voltage Von in response to the voltage change of said input signal, and

said second gate voltage crosses through a voltage level of a threshold voltage of said second output buffer section in response to the voltage change of said input signal after said output voltage of said output buffer circuit reaches said reference voltage Von in response to the voltage change of said input signal.

2. The output buffer circuit according to claim 1,

wherein a difference between time when said first output buffer section starts to output said first output signal and time when said second output buffer section starts to output said second output signal are generated based on a difference between a driving capacity of said first predriver section and a driving capacity of said second predriver section.

3. The output buffer circuit according to claim 2, wherein said first output buffer section includes:

a first p-type transistor, and

a first n-type transistor,

said first predriver section includes;

a first inverter circuit which drives said first p-type transistor, and

a second inverter circuit which drives said first n-type transistor,

said second output buffer section includes;

a second p-type transistor, and

a second n-type transistor,

said second predriver section includes;

a third inverter circuit which drives said second p-type transistor, and

a fourth inverter circuit which drives said second n-type transistor.

4. The output buffer circuit according to claim 1, wherein a size of each of said complementary semiconductors of said first output buffer section is set such that said output voltage of said output buffer circuit reaches said reference voltage in a predetermined time by said first output signal of said first output buffer section, and

a size of each of said complementary semiconductors of said second output buffer section is set such that said output voltage of said output buffer circuit reaches one of a power source voltage and a ground voltage by said first output signal of said first output buffer section and said second output signal of said second output buffer section.

5. The output buffer circuit according to claim 1, wherein a current supplying capacity of said second output buffer section is larger than a current supplying capacity of said first output buffer section.

6. The output buffer circuit according to claim 1, wherein both said first output buffer section and said second output buffer section are CMOS inverters.

7. The output buffer circuit according to claim 1, wherein said threshold voltage of said first output buffer section is a voltage that said first output buffer section starts driving, and

said threshold voltage of said second output buffer section is a voltage that said second output buffer section starts driving.

8. An output buffer circuit comprising:

a first output buffer section which includes complementary semiconductors;

a second output section which includes complementary semiconductors and is connected in parallel with said first output buffer section,

wherein said second output buffer section starts to output a second output signal after a first output signal of said first output buffer section reaches a reference voltage Von indicative of an on-state of an output voltage of said output buffer circuit;

a first predriver section which applies a voltage to a control terminal of said first output buffer section; and

a second predriver section which applies a voltage to a control terminal of said second output buffer section,

wherein a difference between time when said first output buffer section starts to output said first output signal and time when said second output buffer section starts to output said second output signal are generated based on a difference between a driving capacity of said first predriver section and a driving capacity of said second predriver section, and

wherein said driving capacity of said first predriver section is larger than said driving capacity of said second predriver section.

9. An output buffer circuit comprising:

a first output buffer which is connected with an output terminal and includes complementary semiconductors with first gate capacitance;

a second output buffer which is connected with said output terminal and includes complementary semiconductors with second gate capacitance larger than said first gate capacitance;

a first predriver which drives said first output buffer by a first current supplying capacity; and

a second predriver which drives said second output buffer by a second current supplying capacity smaller than said first current supplying capacity,

wherein said second current supplying capacity of said second predriver is set such that said second output buffer drives said output terminal when said first output buffer driven by said first predriver outputs a voltage at said output terminal that reaches a reference voltage Von indicative of one of an on-state and an off-state of said output buffer circuit.

10. The output buffer circuit according to claim 9, wherein both said first predriver and said second predriver are CMOS inverters.

11. The output buffer circuit according to claim 9, wherein said reference voltage is set based on a turn-on voltage of a circuit connected with said output terminal and driven by said output buffer circuit.

12. An output buffer comprising:

a first main buffer which includes;

a first transistor with a first conductive type, which is connected between a first power line and an output terminal, and

a second transistor with a second conductive type, which is connected between a second power line and said output terminal;

a second main buffer which has a larger current driving capacity than said first main buffer and includes;

a third transistor with the first conductive type, which is connected between said first power line and said output terminal, and

a fourth transistor with the second conductive type, which is connected between said second power line and said output terminal; and

a predriver which is connected between an input terminal and control terminals of said first, second, third and fourth transistors, changes a conducting state of one of said first and second transistors into a non-conducting state thereof rapidly, changes the non-conducting state of another of one of said first and second transistors into the conducting state thereof gradually, changes the conducting state of one of said third and fourth transistors into the non-conducting state thereof rapidly, and changes the non-conducting state of another of one of said third and fourth transistors into the conducting state thereof gradually, in response to an input signal supplied to said input terminal,

wherein said predriver makes one of said third and fourth transistors be in the conducting state after a voltage of said output terminal reaches a predetermined voltage level by a corresponding one of said first and second transistors,

wherein said predriver includes;

a first switching element which is connected between said first power line and a control terminal of said first transistor,

a first resistance element which is connected between said control terminal of said first transistor and a control terminal of said second transistor,

a second switching element which is connected between said control terminal of said second transistor and said second power line,

a third switching element which is connected between said first power line and a control terminal of said third transistor,

a second resistance element which is connected between said control terminal of said third transistor and a control terminal of said fourth transistor, and

a fourth switching element which is connected between said control terminal of said fourth transistor and said second power line,

said second resistance element has a larger resistance value than said first resistance element.

13. The output buffer according to claim 12, wherein both said first and second resistance elements are transfer gates.

14. The output buffer according to claim 12, wherein said first, second, third and fourth switching elements are transistors, each of which has said control terminal that receives said input signal.

15. The output buffer according to claim 12, wherein said first and third switching elements are transistors with said first conducting type, and said second and fourth switching elements are transistors with said second conducting type.