Implementation of output floating scheme for hv charge pumps

• US 7,368,979 B2
• Filed: 09/19/2006
• Issued: 05/06/2008
• Est. Priority Date: 09/19/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Pan, Feng, Pham, Trung, Mui, Man, Wang, Chi-Ming, Kwon, Gyuwan, Govindu, Prashanti
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US11/523,875
• Publication Number:
  US 20080068067A1
• Time in Patent Office: 595 Days
• Field of Search: 327/535, 327/536, 327/537
• US Class Current: 327/536
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.

Claims

1. A method of managing power in a non-volatile memory system having a high voltage charge pump and associated regulator, comprising:

receiving an operation command corresponding to an operation;

pumping up a charge pump output voltage to a desired output voltage consistent with the received operation command;

turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage;

compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out; and

compensating for junction leakage by turning on only the regulator until the charge pump output voltage is the desired output voltage.

2. A method as recited in claim 1, wherein the operational command is selected from a group that includes:

PROGRAMMING, ERASE, and VERIFY.

3. A method as recited in claim 2, wherein the desired output voltage is selected from a group that includes;

V_prgm, V_era, and V_pass, wherein V_prgm is approximately 25 volts, V_erase is approximately 15 volts, and V_pass is approximately 10 volts.

4. A method as recited in claim 1, further comprising;

generating a FLAG signal by the regulator having a FLAG signal rising edge and a FLAG signal falling edge;

forwarding the FLAG signal to the charge pump by the regulator; and

detecting a first FLAG signal falling edge immediately after the load is connected to the output node of the high voltage charge pump.

5. A method as recited in claim 4, comprising;

generating a FLAG_ASSIST signal having a FLAG_ASSIST rising edge and FLAG_ASSIST falling edge by the charge pump based upon the detected first FLAG signal falling edge.

6. A method as recited in claim 5, wherein the turning OFF the regulator and the charge pump and the resetting a pump clock rate to a very slow pump clock rate is based upon detecting a first FLAG_ASSIST falling edge.

7. A method as recited in claim 6, wherein the compensating for charge sharing comprises:

turning ON the charge pump only for a first period of time.

8. A method as recited in claim 7, during VERIFY operation, the charge pump output node is floating.

9. A method as recited in claim 1, wherein the slow clock rate is approximately 400 ns.

10. A charge pump circuit used to provide the voltages and currents to a flash memory cell, comprising;

a charge pump used to convert an input voltage (Vin) to a desired output voltage (Vout) at a charge pump output node that is higher than the input voltage Vin;

a regulator circuit that regulates the output of the charge pump so that the output voltage Vout remains at a substantially constant voltage level;

a load_connect_enable signal generator that provides a load_connect_enable signal to a switch 218, wherein when the load_enable_connect signal goes LOW, the switch “

opens”

thereby electrically disconnecting the charge pump output node from a load causing the charge pump output node to float, and wherein when the load_connect_enable signal goes HIGH, then the switch circuit “

closes”

so as to electrically connect the charge pump output node to the load;

a FLAG signal generator unit coupled to the regulator that generates and issues to the charge pump by a FLAG signal having a rising and a falling edge;

a FLAG_ASSIST signal generator unit connected to the charge pump that generates a FLAG_ASSIST signal having a FLAG_ASSIST rising and falling edge; and

an edge detector unit in communication with the FLAG signal generator and the FLAG_ASSIST signal generator wherein the edge detector latches the first falling edge of the FLAG signal immediately after the load_connect_enable signal is HIGH goes HIGH and in response, the FLAG_ASSIST signal generator unit generates a FLAG_ASSIST signal having a FLAG_ASSIST rising and falling edge that is used in conjunction with the FLAS signal to turn off the regulator and the charge pump and in some cases to set the pump clock to a very slow clock rate.

11. A computer program product for managing power in a non-volatile memory system having a high voltage charge pump and associated regulator executed by a computer processor, comprising:

computer code for receiving an operation command corresponding to an operation;

computer code for pumping up a charge pump output voltage to a desired output voltage consistent with the received operation command;

computer code for turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage;

computer code for compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out;

computer code for compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage; and

computer readable medium for storing the computer code.

12. Computer program product as recited in claim 11, wherein the operational command is selected from a group that includes:

PROGRAMMING, ERASE, and VERIFY.

13. Computer program product as recited in claim 12, wherein the desired output voltage is selected from a group that includes;

V_prgm, V_era, and V_pass, wherein V_prgm is approximately 25 volts, V_erase is approximately 15 volts, and V_pass is approximately 10 volts.

14. Computer program product as recited in claim 11, further comprising;

computer code for generating a FLAG signal by the regulator having a FLAG signal rising edge and a FLAG signal falling edge;

computer code for forwarding the FLAG signal to the charge pump by the regulator; and

computer code for detecting a first FLAG signal falling edge immediately after the load is connected to the output node of the high voltage charge pump.

15. Computer program product as recited in claim 14, comprising;

computer code for generating a FLAG_ASSIST signal having a FLAG_ASSIST rising edge and FLAG_ASSIST falling edge by the charge pump based upon the detected first FLAG signal falling edge.

16. Computer program product as recited in claim 15, wherein the turning OFF the regulator and the charge pump and the resetting a pump clock rate to a very slow pump clock rate is based upon detecting a first FLAG_ASSIST falling edge.

17. Computer program product as recited in claim 16, wherein the compensating for charge sharing comprises:

turning ON the charge pump only for a first period of time.

18. Computer program product as recited in claim 17, during VERIFY operation, the charge pump output node is floating.

19. A method as recited in claim 11, wherein the slow clock rate is approximately 400 ns.