Gate driving circuit and display apparatus having the same

• US 7,369,111 B2
• Filed: 04/27/2004
• Issued: 05/06/2008
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong Hwan, Kim, Hyung Guel, Jeon, Jin
• Primary Examiner(s): Tran; My-Chau T.
• Application Number:
  US10/832,631
• Publication Number:
  US 20040217935A1
• Time in Patent Office: 1,470 Days
• Field of Search: 345/55, 345/84, 345/87, 345/98, 345/100, 377/64
• US Class Current: 345/100
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0281 Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3692 suitable for passive matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A liquid crystal display apparatus including a gate driving circuit disposed on a liquid crystal display is provided. The apparatus further includes a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to data lines. The gate driving circuit includes a plurality of stages connected to one another in parallel. The odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal and the even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal.

Claims

1. A gate driving device for applying gate driving signals to gate lines of a liquid crystal display panel, comprising a plurality of stages connected to one another in parallel to apply gate driving signals to gate lines of a liquid crystal display panel, wherein:

a last stage of the stages includes a last control terminal which receives a start signal, and

odd-numbered stages of the stages each output the gate driving signals to odd-numbered gate lines of the gate lines in response to a first clock signal, and even-numbered stages of the stages each output the gate driving signals to even-numbered gate lines of the gate lines in response to a second clock signal, the second clock having an opposite phase from a phase of the first clock signal.

2. The gate driving device according to claim 1, wherein the first and second clock signals each have a high stage during a first half period and a last half period, respectively, and the first and second clock signals each have a low state during the last half period and the first half period, respectively.

3. The gate driving device according to claim 1, wherein each of the stages includes:

a clock signal terminal to receive the first or second clock signal;

a first output terminal to output the gate driving signals in response to the first or second clock signal;

a second output terminal to output a stage driving signal in response to the first or second clock signal;

an input terminal to receive the stage driving signal from a previous stage; and

a control terminal to receive the stage driving signal from a next stage.

4. The gate driving device according to claim 3, wherein the input terminal of a first stage of the stages receives the start signal.

5. The gate driving device according to claim 3, wherein each of the stages further includes:

a ground voltage terminal to receive a ground voltage; and

a driving voltage terminal to receive a driving voltage.

6. The gate driving device according to claim 3, wherein each of the stages further includes:

a first pull-up part to output the first or second clock signal to the first output terminal;

a second pull-up part to output the first or second clock signal to the second output terminal;

a first pull-down part to discharge the first or second clock signal in response to an inactivation of the first pull-up part;

a second pull-down part to discharge the first or second clock signal in response to an inactivation of the second pull-up part;

a pull-up driving part to activate the first and second pull-up parts; and

a pull-down driving part to activate the first and second pull-down parts while inactivating the first and second pull-up parts.

7. The gate driving device according to claim 6,

wherein the first pull-up part includes a first NMOS transistor having a source electrode connected to the clock signal terminal, a drain electrode connected to the first output terminal and a gate electrode connected to the pull-up driving part;

and

wherein the second pull-up part includes a second NMOS transistor having a source electrode connected to the clock signal terminal, a drain electrode connected to the second output terminal and a gate electrode connected to the gate electrode of the first pull-up part.

8. The gate driving device according to claim 6,

wherein the first pull-down part includes a third NMOS transistor having a source electrode connected to a ground voltage terminal, a drain electrode connected to the first output terminal and a gate electrode connected to the pull-down driving part;

and

wherein the second pull-down part includes a fourth NMOS transistor having a source electrode connected to the ground voltage terminal, a drain electrode connected to the second output terminal and a gate electrode connected to the gate electrode of the third NMOS transistor.

9. The gate driving device according to claim 6, wherein the pull-up driving part includes:

a fifth NMOS transistor having a drain electrode connected to a driving voltage terminal, a source electrode connected to the pull-down driving part and a gate electrode connected to the input terminal;

a sixth NMOS transistor having a drain electrode connected to the driving voltage terminal, a source electrode connected to a drain electrode of a seventh NMOS transistor and a gate electrode connected to the driving voltage terminal; and

the seventh NMOS transistor having a source electrode connected to a ground voltage terminal, a drain electrode connected to the source electrode of the sixth NMOS transistor and a gate electrode connected to the first pull-up part.

10. The gate driving device according to claim 9, wherein the pull-down driving part includes:

an eighth NMOS transistor having a drain electrode connected to a driving voltage terminal, a source electrode connected to the first pull-down part and a gate electrode connected to the source electrode of the sixth NMOS transistor;

a ninth NMOS transistor having a source electrode connected to the ground voltage terminal, a drain electrode connected to the first pull-down part and a gate electrode connected to the first pull-up part;

a tenth NMOS transistor having a source electrode connected to the ground voltage terminal, a drain electrode connected to the first pull-up part and a gate electrode connected to the first pull down part; and

a eleventh NMOS transistor having a source electrode connected to the ground voltage terminal, a drain electrode connected to the first pull-up part and a gate electrode connected to the control terminal.

11. The gate driving device according to claim 10, wherein the pull-down driving part further includes a twelfth NMOS transistor having a source electrode connected to the ground voltage terminal, a drain electrode connected to the first pull-down part and a gate electrode connected to the input terminal.

12. A liquid crystal display apparatus, comprising:

a liquid crystal display panel including a plurality of pixels, the pixels having a plurality of gate lines, a plurality of data lines and a plurality of switching elements connected between the gate lines and the data lines;

a gate driving circuit disposed on the liquid crystal display panel and including a plurality of stages connected to one another in parallel, wherein the input terminal of a first stage of the stages receives a start signal, and the control terminal of a last stage of the stages receives the start signal; and

odd-numbered stages of the stages each apply gate driving signals to odd-numbered gate lines of the gate lines, in response to a first clock signal; and

even-numbered stages of the stages each apply the gate driving signals to even-numbered gate lines of the gate lines, in response to a second clock signal having an opposite phase from a phase of the first clock signal; and

a data driving chip, disposed on the liquid crystal display panel, to apply data driving signals to the data lines.

13. The liquid crystal display apparatus according to claim 12, wherein the gate driving circuit includes:

a clock signal terminal to receive the first or second clock signal;

a first output terminal to output the gate driving signals in response to the first or second clock signal;

a second output terminal to output a stage driving signal in response to the first or second clock signal;

an input terminal to receive the stage driving signal from a previous stage; and

a control terminal to receive the stage driving signal from a next stage.

14. The liquid crystal display apparatus according to claim 12, wherein each of the stages further includes:

a ground voltage terminal to receive a ground voltage; and

a driving voltage terminal to receive a driving voltage.

15. The liquid crystal display apparatus according to claim 14, wherein the data driving chip provides the start signal, the ground voltage, the driving voltage and the first or second clock signal to the gate driving circuit.

16. The liquid crystal display apparatus according to claim 15, further comprising:

a flexible printed board electrically connected to the data driving chip to output the start signal, the ground voltage, the driving voltage, the first or second clock signal and a data signal to the data driving chip.

17. A liquid crystal display apparatus, comprising:

a liquid crystal display panel including a plurality of gate lines and a plurality of data lines;

a first gate driving circuit including a plurality of first stages connected to one another in parallel and disposed on the liquid crystal display panel, the first stages outputting first gate driving signals to odd-numbered gate lines of the gate lines with a blank period, wherein a last stage of the first stages includes a last control terminal which receives a first start signal;

a second gate driving circuit including a plurality of second stages connected to one another in parallel and disposed on the liquid crystal display panel, the second stages outputting second gate driving signals to even-numbered gate lines of the gate lines during the blank period; and

a data driving chip, disposed on the liquid crystal display panel, to output data driving signals to the data lines.

18. The liquid crystal display apparatus according to claim 17, wherein each of the first stage includes:

a clock signal terminal to receive a first clock signal or a second clock signal having a different phase from a phase of the first clock signal;

a first output terminal to output the first gate driving signals in response to the first or second clock signal;

a second output terminal to output a first stage driving signal in response to the first or second clock signal;

an input terminal to receive the first stage driving signal from a previous first stage; and

a control terminal to receive the first stage driving signal from a next first stage.

19. The liquid crystal display apparatus according to claim 18, wherein:

the first clock signal is at a high state during a first quarter period of a full period and is at a low state during a second quarter period, a third quarter period and a fourth quarter period of the full period, and

the second clock signal is at a high state during the third quarter period of the full period and is at a low state during the first quarter period, the second quarter period and the fourth quarter period of the full period.

20. The liquid crystal display apparatus according to claim 19, wherein the first clock signal is applied to the clock signal terminal of odd-numbered stages of the first stages, and the second clock signal is applied to the clock signal terminal of even-numbered stages of the first stages.

21. The liquid crystal display apparatus according to claim 20, wherein each of the second stages includes:

a clock signal terminal output to receive a third clock signal or a fourth clock signal having an opposite phase from a phase of the third clock signal;

a first output terminal to output the second gate driving signals in response to the third or fourth clock signal;

a second output terminal to output a second stage driving signal in response to the third or fourth clock signal;

an input terminal to receive the second stage driving signal from a previous second stage; and

a control terminal to receive the second stage driving signal from a next second stage.

22. The liquid crystal display apparatus according to claim 21, wherein:

the third clock signal is at a high state during the second quarter period of the full period and is at a low state during the first quarter period, the third quarter period and the fourth quarter period of the full period, and

the fourth clock signal is at a high state during the fourth quarter period of the full period arid is at a low state during the first quarter period, the second quarter period and the third quarter period of the full period.

23. The liquid crystal display apparatus according to claim 22, wherein the third clock signal is applied to the clock signal terminal of odd-numbered stages of the second stages, and the fourth clock signal is applied to the clock signal terminal of even-numbered stages of the second stages.

24. The liquid crystal display apparatus according to claim 17, wherein each of the second stages outputs the second gate driving signals delayed by a quarter period with respect to the first gate driving signals output from a corresponding one of the first stages.

25. The liquid crystal display apparatus according to claim 17, wherein the data driving chip applies a first gate control signal to the first gate driving circuit and applies a second gate control signal to the second gate driving circuit, wherein the first gate control signal includes the first start signal and the second gate control signal includes a second start signal.

26. A liquid crystal display apparatus, comprising:

a liquid crystal display panel including a plurality of gate lines and a plurality of data lines;

a first gate driving circuit including a plurality of first stages connected to one another in parallel and disposed on the liquid crystal display panel, the first stages outputting first gate driving signals having a first dummy period and a first active period following the first dummy period to odd-numbered gate lines of the gate lines, wherein a last stage of the first stages includes a last control terminal which receives a first start signal;

a second gate driving circuit including a plurality of second stages connected to one another in parallel and disposed on the liquid crystal display panel, the second stages outputting second gate driving signals having a second dummy period and a second active period following the second dummy period to even-numbered gate lines of the gate lines; and

a data driving chip, disposed on the liquid crystal display panel, to output data driving signals to the data lines during the first and second active periods.

27. The liquid crystal display apparatus according to claim 26, wherein each of the first stages includes:

a clock signal terminal to receive a first clock signal or a second clock signal having an opposite phase from a phase of the first clock signal;

a first output terminal to output the first gate driving signals in response to the first or second clock signal;

a second output terminal to output a first stage driving signal in response to the first or second clock signal;

an input terminal to receive the first stage driving signal from a previous first stage; and

a control terminal to receive the first stage driving signal from a next first stage.

28. The liquid crystal display apparatus according to claim 27, wherein:

the first clock signal is at a high state during a first quarter period and a second quarter period of a full period, and is at a low state during a third quarter period and a fourth quarter period of the full period,

and the second clock signal is at a low state during the first quarter period and the second quarter period of a full period, and is at a high state during the third quarter period and the fourth quarter period of the full period.

29. The liquid crystal display apparatus according to claim 28, wherein the first clock signal is applied to the clock signal terminal of odd-numbered stages of the first stages, and the second clock signal is applied to the clock signal terminal of even-numbered stages of the first stages.

30. The liquid crystal display apparatus according to claim 28, wherein each of the second stage includes:

a clock signal terminal to receive a third clock signal or a fourth clock signal having an opposite phase from a phase of the third clock signal;

a first output terminal to output the second gate driving signals in response to the third or fourth clock signal;

a second output terminal to output a second stage driving signal in response to the third or fourth clock signal;

an input terminal to receive the second stage driving signal from a previous second stage; and

a control terminal to receive the second stage driving signal from a next second stage.

31. The liquid crystal display apparatus according to claim 30, wherein:

the third clock signal is at a high state during the second quarter period and the third quarter period of the full period, and is at a low state during the first quarter period and the fourth quarter period of the full period, and

the fourth clock signal is at a low state during the second quarter period and the third quarter period of the full period, and is at a high state during the first quarter period and the fourth quarter period of the full period.

32. The liquid crystal display apparatus according to claim 26, wherein the first active period of the first gate driving signals output from one of the first gate driving circuit is overlapped with the second dummy period of the second gate driving signals output from a corresponding one of the second gate driving circuit.

33. The liquid crystal display apparatus according to claim 26, wherein the gate driving chip applies a first gate control signal to the first gate driving circuit and applies a second gate control signal to the second gate driving circuit, wherein the first gate control signals include the first start signal and the second gate control signals include a second start signal.