Training pattern for a biased clock recovery tracking loop

• US 7,369,634 B2
• Filed: 09/07/2004
• Issued: 05/06/2008
• Est. Priority Date: 09/07/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vogt, Pete D., Panikkar, Adarsh, Vakil, Kersi H.
• Primary Examiner(s): Liu; Shuwang
• Assistant Examiner(s): HUANG, DAVID S
• Application Number:
  US10/935,903
• Publication Number:
  US 20060050822A1
• Time in Patent Office: 1,337 Days
• Field of Search: 375/354
• US Class Current: 375/354
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.

Claims

1. A method for a biased clock recovery tracking loop comprising:

receiving header information in a training sequence;

receiving control information in the training sequence;

receiving a clock training pattern in the training sequence; and

decoding data encoded in the control information while deriving a clock from the training sequence wherein receiving the control information further comprises;

receiving a first sequence of data, the first sequence of data alternating between a first state and a second state; and

receiving a second sequence of data, the second sequence of data alternating between a constant state and one of a plurality of portions of the encoded data.

2. The method of claim 1 further comprising, decoding the training sequence and aligning a header for a biased tracking loop.

3. The method of claim 1 wherein the header information includes a string of values in the first state to identify the start of a training sequence.

4. The method of claim 3 wherein the header information includes nine consecutive values equal to one.

5. The method of claim 1 wherein the control information comprises a high transition density.

6. The method of claim 1 wherein the constant state is a high logic state.

7. An apparatus comprising:

a link to receive a training sequence containing encoded data; and

a circuit coupled with the link, the circuit to recover clocking information and the encoded data from the training sequence with a biased clock recovery tracking loop wherein;

the training sequence includes a header, control information, and a clock training pattern; and

the control information includes;

a first sequence of data, the first sequence of data alternating between a first state and a second state; and

a second sequence of data, the second sequence of data alternating between a constant state and one of a plurality of portions of the encoded data.

8. The apparatus of claim 7, wherein the training sequence further comprises header information to identify the start of a training sequence.

9. A host controller comprising:

a link to send a training sequence containing encoded data; and

a circuit coupled with the link, the circuit to provide clocking information in a training sequence and to encode data in the training sequence wherein;

the training sequence includes a header, control information, and a clock training pattern; and

the circuit is configured to encode the control information such that the control information includes;

a first sequence of data, the first sequence of data alternating between a first state and a second state; and

a second sequence of data, the second sequence of data alternating between a constant state and one of a plurality of portions of the encoded data.

10. The host controller of claim 9, wherein the training sequence further comprises header information to identify the start of a training sequence.

13. The host controller of claim 9, wherein:

the header includes a plurality of bits in the first state; and

the clock training pattern includes a plurality of bits alternating between the first state and the second state.

11. A system comprising:

a general purpose processor; and

a host controller coupled with the general purpose processor, the host controller comprising;

a link to send a training sequence containing encoded data; and

a circuit coupled with the link, the circuit to provide clocking information in a training sequence to encode data in the training sequence wherein;

the training sequence includes a header, control information, and a clock training pattern; and

the circuit is configured to encode the control information such that the control information includes;

a first sequence of data, the first sequence of data alternating between a first state and a second state; and

a second sequence of data, the second sequence of data alternating between a constant state and one of a plurality of portions of the encoded data.

12. The system of claim 11, wherein the training sequence further comprises header information to identify the start of a training sequence.